`include "def.h" module rfile ( input clk, input [`REG_W-1:0] aadr, badr, cadr, output [`DATA_W-1:0] a, b, input [`DATA_W-1:0] c, input we); reg [`DATA_W-1:0] rf[0:`REG-1]; assign a = rf[aadr]; assign b = rf[badr]; always @(posedge clk) if(we) rf[cadr] <= c; endmodule