[English / Japanese]

Ryuta Kawano



Amano-Lab, Dept. of Information and Computer Science, Keio University

Keywords: Interconnection Networks, Network-on-Chips, High Performance Computing, Low-latency Network Topology

(Last updated 2017-9-22)

Biography


Journal (International)

  1. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Layout-Oriented Routing Method for Low-Latency HPC Networks", IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.xx–xx, Dec 2017. (to appear)

  2. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano, "Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator", IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.xx–xx, Dec 2017. (to appear)

  3. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing", IEICE Transactions on Information and Systems, Vol.E100-D, No.8, pp.1798–1806, Aug 2017.


International conference

  1. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies", Proc. of the IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS'17), pp.xx–xx, Dec 2017. (to appear)

  2. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "LOREN: A Scalable Routing Method for Layout-conscious Random Topologies", Proc. of the 4th International Symposium on Computing and Networking (CANDAR'16), pp.9–18, Nov 2016. [Paper] (Best Paper Award)

  3. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano, "Body bias grain size exploration for a coarse grained reconfigurable accelerator", Proc. of the 26th International Conference on Field-Programmable Logic and Applications (FPL'16), Poster session, pp.330–333, Aug 2016.

  4. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free", Proc. of the 15th IEEE/ACIS International Conference on Computer and Information Science (ICIS'16), pp.565–570, Jun 2016. [Paper]

  5. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Optimized Core-links for Low-latency NoCs", Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'15), pp.172–176, Mar 2015. [Paper] [Slide]

  6. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", The Poster Session at the 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Poster No.15, Apr 2014. (Featured Poster Award)

  7. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Low Latency Network Topology Using Multiple Links at Each Host", The Poster Session at the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Poster session, Poster No.18, Apr 2013. [Poster]


Journal (Japanese domestic)

  1. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "The Study of Low-latency On-chip Topology using Multiple Core Links", IEICE Transactions on Information and Systems, Vol.J97-D, No.3, pp.601–613, Mar 2014.


Japanese domestic conference/meeting

  1. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Routing Method based on Turn Model for Irregular Networks", IEICE Technical Reports CPSY2017-xxx, Vol.xxx, No.xxx, pp.xxx–xxx, Nov 2017. (to appear)

  2. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Scalable Routing Method for Random Topologies with the Link Length Limited", Proc. of the 15th Forum on Information Technology, Vol.1, pp.337–338, Sep 2016.

  3. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "An Effective Virtual Channel Allocation Method for Deterministic Deadlock-free Routing", IEICE Technical Reports CPSY2015-148, Vol.115, No.518, pp.163–168, Mar 2016.

  4. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Easily implementable routing algorithms for irregular topologies in offchip interconnects", Proc. of the 78th National Convention of IPSJ, pp.1:15–1:16, Mar 2016.

  5. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "A Low Latency Distributed Routing Method for Random Topologies in HPC Networks", IEICE Technical Reports CPSY2015-103, Vol.115, No.374, pp.105–110, Dec 2015. [Slide] (IEICE ICD Young Presentation Award)

  6. Hiroshi Nakahara, Daichi Fujiki, Seiichi Tade, Ryota Yasudo, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Koji Nakano, Hideharu Amano, "Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint", IEICE Technical Reports CPSY2015-104, Vol.115, No.374, pp.111–116, Dec 2015.

  7. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches", IEICE Technical Reports CPSY2014-20 (SWoPP'14), Vol.114, No.155, pp.61–66, Jul 2014.

  8. Seiichi Tade, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Alterable uniform and random NoC through rewiring", IEICE Technical Reports CPSY2014-22 (SWoPP'14), Vol.114, No.155, pp.73–78, Jul 2014.

  9. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "HPC interconnect for high topological embeddability by supplementary optical circuit switches", IEICE Technical Reports CPSY2013-111, Vol.113, No.497, pp.253–258, Mar 2014.

  10. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", IEICE Technical Reports RECONF2013-77, Vol.113, No.418, pp.125–130, Jan 2014.

  11. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "A Low Latency Topology for NoC Using Multiple Host Links", IEICE Technical Reports CPSY2013-9, Vol.113, No.21, pp.49–54, Apr 2013. (IEICE CPSY Young Presentation Award)

  12. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Low Latency Network Topology Using Multiple Links at Each Host", IEICE Technical Reports CPSY2012-75, Vol.112, No.376, pp.123–128, Jan 2013.


Awards

  1. "Best Paper Award", The 4th International Symposium on Computing and Networking (CANDAR'16). [Photo]

  2. "IEICE ICD Young Presentation Award" (2016).

  3. "IEICE CPSY Young Presentation Award" (2013).

Nomination

For co-authors

  1. Seiichi Tade, "Featured Poster Award", The 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII).


Acknowledgment

A part of our work is supported by JST CREST, a Grant-in-Aid for Young Scientists (B) from JSPS KAKENHI, JSPS KAKENHI S Grant Number 25220002, JSPS KAKENHI Grant Number 15J03374, National Institute of Informatics (NII) Publicly Offered Collaborative Research (General Research), and SCOPE R&D to foster young ICT researchers.