[English / Japanese]

Seiichi Tade



Amano-Lab, Dept. of Information and Computer Science, Keio University

Keywords: Interconnection networks, Network-on-Chips, High performance computing, Topology, Jazz Guitar

(Last updated 2015-5-20)

Biography


Journal (International)


International conference

  1. Seiichi Tade, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Metamorphotic Network-on-Chip for Various Types of Parallel Applications", to appear in Proc. of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'15), pp.xxx-xxx, Toronto, Canada, July 2015.

  2. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Optimized Core-links for Low-latency NoCs", Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'15), pp.xx–xx, Mar 2015. (to appear)

  3. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", The Poster Session at the 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Poster No.15, Apr 2014. (Featured Poster Award)


Journal (Japanese domestic)


Japanese domestic conference/meeting

  1. Seiichi Tade, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Alterable uniform and random NoC through rewiring", IEICE Technical Reports CPSY2014-22 (SWoPP'14), Vol.114, No.155, pp.73–78, Jul 2014.

  2. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", IEICE Technical Reports RECONF2013-77, Vol.113, No.418, pp.125–130, Jan 2014.


Award

  1. "IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Featured Poster Awerd" (2014).

Nomination

For co-authors


Acknowledgment

A part of our work is supported by JST CREST, and a Grant-in-Aid for Young Scientists (B) from JSPS KAKENHI