Publications

International Journal Papers
  1. [IEEE TPDS] Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, and Hideharu Amano, "Designing High-Performance Interconnection Networks with Host-Switch Graphs", IEEE Transactions on Parallel and Distributed Systems, vol. 30, no. 2, pp. 315-330, February 2019. (Date of Publication on IEEE Xplore: 07 August 2018)
    [IEEE Xplore] [Paper]
  2. [IEEE TC] Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, "Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers", IEEE Transactions on Computers., vol. 66, no. 4, pp. 702-716, April 2017. (Date of Publication on IEEE Xplore: 07 September 2016)
International Conference/Symposium Proceedings
  1. [FPT'18] Ryota Yasudo, Jose Gabriel Figueiredo Continho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, and Tobias Becker, "Performance Estimation for Exascale Reconfigurable Dataflow Platforms", in Proc. of the International Conference on Field-Programmable Technology, Naha, Japan, December 2018.
  2. [CANDAR'18] Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, and Hideharu Amano, "k-Optimized Path Routing for High-Throughput Data Center Networks", in Proc. of the Sixth International Symposium on Computing and Networking, Hida Takayama, Japan, November 2018. (Outstanding Paper Award)
  3. [FCCM'18] Ryota Yasudo, Ana Lucia Varbanescu, Jose Gabriel Figueiredo Coutinho, Wayne Luk, and Hideharu Amano, "Performance Prediction for Large-scale Heterogeneous Platforms", in Proc. of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, USA, April/May 2018.
  4. [ICPADS'17] Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, "HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies", in Proc. of the IEEE 23rd International Conference on Parallel and Distributed Systems, pp. 664-673, Shenzhen, China, December 2017. (Acceptance rate: 89/271 = 32.8%)
  5. [NOCS'17] Hiroshi Nakahara, Nguyen Anh Vu Doan, Ryota Yasudo, and Hideharu Amano, "XYZ-Randomization using TSVs for Low-Latency Energy-Efficient 3D-NoCs", in Proc. of the 11th International Symposium on Networks-on-Chip (co-located with Embedded Systems Week), Article no. 17, Seoul, South Korea, October 2017. (Acceptance rate: 12/44 = 31.8%)
  6. [ICPP'17] Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, and Hideharu Amano, "Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks", in Proc. of the 46th International Conference on Parallel Processing, pp.322-331, Bristol, United Kingdom, August 2017. (Acceptance rate: 60/211 = 28.4%)
    [Paper] [Slides]
  7. [I-SPAN'17] Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, and Michihiro Koibuchi, "3D layout of Spidergon, Flattened Butterfly and Dragonfly on a chip stack with inductive coupling through chip interface", in Proc. of the 14th International Symposium on Pervasive Systems, Algorithms, and Networks, IEEE Computer Society Press, pp.52-59, Exeter, Devon, United Kingdom, June 2017.
  8. [NOCS'15] Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, "On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck", in Proc. of the 9th ACM/IEEE International Symposium on Networks-on-Chip, Article No. 16, pp.1-8, Vancouver, BC, Canada, September 2015. (Acceptance rate: 18/73 = 24.7%)
  9. [NOCS'14] Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, and Tadao Nakamura, "Design of a Low Power NoC Router Using Marching Memory Through Type", in Proc. of the 8th IEEE/ACM International Symposium on Networks-on-Chip, pp.111-118, Ferrara, Italy, September 2014. (Acceptance rate: 21/83 = 25.3%)
  10. [COOL Chips'14] Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, and Tadao Nakamura, "A low power NoC router using the marching memory through type", in Proc. of the17th IEEE Symposium on Low-Power and High-Speed Chips, pp.1-3, Yokohama, Japan, April 2014.
Japanese Domestic Conference/Meeting Proceedings
  1. [IEICE-CPSY/IPSJ-ARC] 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "高スループットな相互結合網のためのスケーラブルな複数経路選択手法", 電子情報通信学会技術研究報告 (Design Gaia'18), 広島市, 広島, 2018年12月.
  2. [IEICE-CPSY/IPSJ-ARC] 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "ルーティングアルゴリズムによる通信帯域の測定と理解", 電子情報通信学会技術研究報告, vol. 118, no. 165, CPSY2018-23, pp. 133-138 (SWoPP'18), 熊本市, 熊本, 2018年7月.
  3. [IEICE-CPSY/IPSJ-ARC] 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "ターンモデルベースの不規則網向けルーティング", 電子情報通信学会技術研究報告, vol. 117, no. 278, CPSY2017-44, pp. 23-28 / 情報処理学会研究報告, vol. 2017-ARC-228, no. 6, pp. 1-6, (Design Gaia'17), 熊本市, 熊本, 2017年11月.
  4. [IEICE-COMP] 安戸僚汰, 鯉渕道紘, 天野英晴, 中野浩嗣, "ホストとスイッチから成る相互結合網の理論モデル", 電子情報通信学会技術研究報告, vol. 116, no. 381, COMP2016-40, pp. 51-58, 東広島市, 広島, 2016年12月.
  5. [IEICE-CPSY/IPSJ-ARC] 安戸僚汰, 藤原一毅, 鯉渕道紘, 松谷宏紀, 天野英晴, 中村維男, "非正則グラフによる低遅延相互結合網の検討", 電子情報通信学会技術研究報告, vol. 116, no. 177, CPSY2016-39, pp. 281-286 / 情報処理学会研究報告, vol. 2016-ARC-221, no. 44, pp. 1-6 (SWoPP'16), 松本市, 長野, 2016年8月.
  6. [IEICE-CPSY/IPSJ-ARC] 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, "分散ルータによる高性能NoC", 電子情報通信学会技術研究報告, vol. 115, no. 399, CPSY2015-127, pp. 149-154 / 情報処理学会研究報告, vol. 2016-ARC-218, no. 26, pp. 1-6, 横浜市, 神奈川, 2016年1月. (情報処理学会 山下記念研究賞 受賞)
  7. [IEICE-CPSY] 中原浩, 藤木大地, 蓼誠一, 安戸僚汰, 河野隆太, 松谷宏紀, 鯉渕道紘, 中野浩嗣, 天野英晴, "三次元積層チップにおける最大配線長制限下トポロジ最適化", 電子情報通信学会技術研究報告, vol. 115, no. 374, CPSY2015-104, pp. 111-116, 京都市, 京都, 2015年12月.
  8. [IEICE-CPSY/IPSJ-ARC] 中原浩, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, "三次元積層チップへの高性能既存トポロジレイアウト法", 電子情報通信学会技術研究報告, vol. 115, no. 174, CPSY2015-43, pp. 275-280 / 情報処理学会研究報告, vol. 2015-ARC-16, no. 42 (SWoPP'15), pp. 1-6, 別府市, 大分, 2015年8月.
  9. [IEICE-CPSY] 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, "トランスペアレントラッチを用いたNoC向け分散ルータアーキテクチャ", 電子情報通信学会技術研究報告, vol. 114, no. 330, CPSY2014-80 (Design Gaia'14), pp. 45-50, 別府市, 大分, 2014年11月.
  10. [IEICE-CPSY] 安戸僚汰, 加賀美崇紘, 天野英晴, 中瀬泰伸,渡邊政志, 大石 司, 清水 徹, 中村維男, "マーチングメモリスルータイプを用いたNoCルータ", 電子情報通信学会技術研究報告, vol. 113, no. 324, CPSY2013-71 (Design Gaia'13), pp. 71-76, 鹿児島市, 鹿児島, 2013年11月.
Invited Talks
  1. [CANREXI] Ryota Yasudo, "Interconnection Networks with the Optimal Number of Switches and the Optimal Host Distribution", CANREXI (CANDAR Extreme Infrastructure Workshop), December 2018.
Others