研究業績

論文誌

  1. Y.Matsushita, H.Okuhara, K.Masuyama, Y.Fujita, R.Kawano, H.Amano, “Body Bias Domain Partitioning
    Size Exploration for a Coarse Grained Reconfigurable Accelerator,” IEICE Trans. on Information and Systems, 2017 (Accepted)
  2. A.Nomura, Y.Matsushita, J.Kadomoto, H.Matsutani, T.Kuroda, H.Amano, “Escalator Network for a
    3D Chip Stack with Inductive Coupling ThruChip Interface,” International Journal of Network and Computing, (Accepted)
  3. T.Okubo, M.Sit, H.Amano, R.Takata, R.Sakamoto, M.Kondo,
    “A Software Development Environment for a Multi-chip Convolutional Network Accelerator,”
    International Journal of Computer Application, Vol.24, No.2, June 2017.
  4. H.Okuhara, Y.Fujita, K.Usami, H.Amano,
    “Power Optimization Methodology for Ultra Low Power Microcontroller with Silicon on Thin BOX MOSFET,”
    IEEE Transaction on VLSI systems, Vol.25, No.4, 1578-1582, 2017, DOI:10.1109/TVLSI.2016.2635675
  5. R.Yasudo, H.Matsutani, M.Koibuchi, H.Amano, T.Nakamura,
    “Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers,” IEEE Transaction on Computers, Vol.66, No.4, pp.702-716, DOI:10.1109/TC.2016.2606597, 2017.
  6. 宇佐美公良, “超低電圧LSIの設計技術,” 電子情報通信学会Fundamentals Review Vol.10,No.3 p.195-205, 2016
  7. Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano,
    Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura and Mitaro Namiki:
    An Operating System Guided Fine-Grained Power Gating Control Based on
    Runtime Characteristics of Applications, Vol.E99-C, No.8, pp.926-935
    (2016-08-01)
  8. A.B.Ahmed, H.Matsutani, M.Koibuchi, K.Usami, H.Amano,
    “Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems,” IEICE Trans. Electron, Vol.E99-C, No.8, pp.909-917, Aug.2016.
  9. H.Nakahara, T.Ozaki, H.Matsutani, M.Koibuchi, H.Amano, “Novel Chips Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface,”
    IEICE Trans. Inf.& Syst. Vol.E99-D No,12, pp.2871-2880, Dec.2016, DOI: 10.1587/transinf.2016PAP0033.
  10. 奥原颯、天野英晴、”Silicon on Thin BOX MOSFET を用いた動的基板バイアス制御の効果と実装の検討,”
    情報処理学会論文誌、Vol.57, No.2 pp.708-717,2016
  11. 坂本龍一, 佐藤未来子, 並木美太郎: マルチコアアクセラレータのパイプライン並列処理のため
    のOpenCL実行環境, 電子情報通信学会論文誌D, Vol.J98-D, No.11, pp.1377-1389.
  12. Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Nnamiki, “A Fine-grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units,” IEICE Transactions on Electronics Vol.E98-C, No.7, pp.559-568(2015-07-01)
  13. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, “Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces,” IEEE Transaction on VLSI systems, Vol.24, No.2, pp.493-506,2016.
  14. Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano, “A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA,” International Journal of Networking and Computing, vol.5, No.1 pp.239-251, Jan. 2015.
  15. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda and Hideharu Amano, “3D NoC with Inductive-Coupling Links for Building-Block SiPs”, IEEE Transaction on Computers, Vol.63, No.3, pp.748–763,March 2014 (10.1109/TC.2012.249)
  16. Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo and Hiroshi Nakamura, “A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC”, IEEE Micro, Vol.33, Issue 6, pp.6-15, Nov/Dec. 2013 (10.1109/MM/2013.12)
  17. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, “Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs”, IPSJ Transactions on SLDM Vol.7, pp.27-36 (10.2197/ipsjtsldm.7.27)
  18. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, “Vertical Link On/Off Regulations for Inductive- Coupling Based Wireless 3-D NoCs”, IEICE transaction on Information and Systems, Vol.E96-D, No.12, pp.2753-2764, 2013.(10.1587/transinf.E96.D.2753)

国際学会（Keynote/Invited/Tutorial/Special Session）

  1. Hideharu Amano, “A building block computing system for AI applications”, Keynote Speech of McSoC2017
  2. Tadahiro Kuroda, “Near-Field Coupling Integration Technology”, Keynote speech of NOCS2016
  3. Hiroki Matsutani, “Inductive-Coupling 3D Wireless NoC Designs”, The 29th International Conference on VLSI Design (VLSID’16), Special Session (Video presentation), Jan 2016.
  4. H.Amano, “Building Block Computing Systems using Reconfigurable Accelerators,” Keynote of the 1st RIS-MJIIT Workshop on Renewable and Sustainable Integrated Systems,” Dec. 2015.
  5. Y. Take, J. Kadomoto, and T. Kuroda,”3D Integration Using Inductive Coupling and Coupled Resonator (Invited),“2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT2015), Proceedings, pp. 46-48, Aug. 2015.
  6. T.Kuroda, “3D Integration by Inductive Coupling”, CICC, Session 11-3, Sept. 2014
  7. H.Matsutani “3D Wireless NoC Architectures”, NOCS2014, Sept.2014.
  8. D.Ditzel, T.Kuroda, S.Lee, “Low-Cost 3D Chip Stacking with ThruChip Wireless Connections”, Hot Chips, Aug.2014.
  9. H.Amano “Building Block Computing Systems with Wireless Inductive Through Chip Interface”, D43D, June.2014.
  10. H.Matsutani “3D WiNOC Architectures”, DATE2014, March, 2014.
  11. H.Matsutani “3D Wireless NoC architectures”, NoCS2014, Special Session, 2014.9.17-19, Ferrara, Italy
  12. Masaaki Kondo, “Evaluating Power-Efficiency for an Embedded Microprocessor with Fine-Grained Power-Gating”, 14th International Forum on Embedded MPSoC and Multi-core, Margaux, France, July 7-11, 2014.

国際学会（査読付き）

  1. C. Cortes, H.Amano, “Break Even Time Analysis Using Empirical Overhead Parameters for Embedded Systems on SOTB Technology,” Design of Circuits and Integrated Systems Conference, Nov. 2017
  2. H.Nakahara, N.A.V.Doan, R.Yasudo, H.Amaon, “XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs,” NOCS2017, Oct. 2017
  3. K.Usami, S.Kogure, Y.Yoshida, R.Magasaki, H.Amano, “Level-shifter Free Approach for Multi-VDD SOTB employing Adaptive Vt Modulation for pMOSFET,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Oct. 2017
  4. N.A.V.Doan, Y.Matsushita, N.Ando, H.Okuhara, H.Amano, “Multi-Objective Optimization for Application Mapping and Body Boas COntrol on a CGRA,” IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Sept. 2017
  5. R.Sakamoto, R.Takata, J.Ishii, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano, “The Design and Implementation of Scalable Deep Neural Network Accelerator Cores,”IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Sept. 2017
  6. T.Kojima, N.Ando, H.Okuhara, N.A.V.Doan, H.Amano, “Body Bias Optimization for Variable Pipelined CGRA”, International Conference on Field Programmable Logic and Application (FPL2017), Sept. 2017.
  7. H.Nakahara, R.Yasudo, H.Matsutani, H.Amano, H.Koibuchi, “3D layout of Spidergon, Flattened Butterfly and Dragonfly on a chip stack with inductive coupling through chip interface,” The 14th International Symposium on Pervasive Systems, Algorithms, and Networks (I-SPAN2017), June, 2017.
  8. C.Cortes, H.Amano, “Switching Region Analysis for SOTB Technology,” 10th International Caribbean Conference on Devices, Circuits and Systems, June. 2017
  9. T.Ohkubo, R.Takata, R.Sakamoto, M.Kondo, H.Amano, “NAMACHA: A software edevelopment environment for a mutli-chip convolutional network accelerator,” CATA2017, March 2017
  10. H.Okuhara, A.B.Ahmed, J.M.Kuehn, H.Amano, “Leveraging Asymmetric Body Boas Control for Low Power LSI Design,” IEEE CoolChips20. April 2017
  11. K.Azegami, H.Okuhara, H.Amano, “Body Bias Control for Renewable Energy Source with a High Inner Resistance,” IEEE CoolChips20, April 2017
  12. S. Hamada, A. Koshiba, M. Namiki, “Basic Design of OS
    Scheduler for SOTB CPU “GC-SOTB” to Reduce Power Consumption,”
    IEEE Symposium on Low-Power and High-Speed Chips(CoolChips) 20,
    Poster 5(2017-04-20)
  13. A. Koshiba, R. Sakamoto, and M. Namiki, “Operating System Support for
    Fine-grained Pipeline Parallelism on Heterogeneous Multicore Accelerators,”
    The European Conference on Computer Systems (EuroSys) 2017, Poster, (2017-04)
  14. Atsushi Koshiba, Linzhan Guo, Mikiko Sato, and Mitaro Namiki:
    Energy-saving Control based on Dynamic Prediction with Exponential
    Smoothing on KVM Virtualized Environments, Poster 15,
    IEEE Symposium on Low-Power and High-Speed Chips(Cool Chips XIX)
    (2016-04-21)
  15. Pornpat Paethong, Mikiko Sato and Mitaro Namiki:
    Low-power distributed NoSQL database for IoT middleware,
    2016 Fifth ICT International Student Project Conference (ICT-ISPC),
    pp.158-161 (2016-05)
  16. N.Ando, K.Masuyama, H.Okuhara, H.Amano, “Variable Pipeline Structure for Coarse Grained Reconfigurable Array CMA,” ICFPT2016, Dec.2016
  17. J. Kadomoto, T. Miyata, H. Amano, T. Kuroda, “An Inductive-Coupling Bus with Collision Detection Scheme
    Using Magnetic Field Variation for 3-D Network-on-Chips”, A-SSCC’16, Nov. 2016
  18. A.Nomura, H.Matsutani, J.Kadomoto, T.Kuroda, “Vertical Packet Switching Elevator Network using Inductive Coupling ThruChip Interface,” CANDAR2016,pp.195-201, DOI:10.1109/CANDAR.2016.0043, 2016
  19. J.Kadomoto, T.Miyata, H.Amano, T.Kuroda, “An Inductive_coupling Bus with Collision Detection Scheme Using Magnetic Field Variation for 3-D Network-on-Chips,” ASSCC2016 (To appear)
  20. Y.Matsusita, H.Okuhara, K.Masuyama, Y.Fujita, R.Kawano, H.Amano, “Body Bias Grain Size Exploration for a Coarse Grained Reconfigurable Accelerator,” The 26th International Conference on Field_Programmable Logic and Applications, pp.1-4, DOI:10.1109/FPL.2016.7577346,Sept. 2016.
  21. J.M.Kuehn, H.Amano, O.Bringmann, W.Rosenstiel, “Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search”, Proc. of the 53nd Design Automation Conference, Junly pp.1-6, DOI: 10.1145/2897937.2898039, 2016.
  22. R.Kawano, H.Nakahara, S.Tade, I.Fujiwara, H.Matshutani, M.Koibuchi, H.Amano, “ACRO: Assigning of Channels in Reverse Oprder to Make Arbitrary Routing Deadlock free,” The 15th IEEE/ACIS International Conference on Computer and Information Science (ICIS), July, 2016.
  23. Lin-Zhan GUO, MikikoSato, MitaroNamiki: Energy-Saving Control Based on Energy Prediction in KVM
    Virtualized Environments: The 2015 4th ICT International Student Project Conference (ICT-ISPC 2015).
  24. Koichiro Masuyama, Yu Fujita, Hayate Okuhara and Hideharu Amano, “A 297MOPS/0.4mW Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA-SOTB-2″, Proc. of The 10th International Conference on ReConFigurable Computing and FPGAs, Dec. 2015
  25. Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano, “Trax Solver on Zynq with Deep Q-Network”, Proc. of the International Conference on Field-Programmable Technology (ICFPT), December 2015.
  26. Yu Fujita, Hayate Okuhara, Koichiro Masuyama, and Hideharu Amano, “Power optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB”, Proc. of The Third International Symposium on Computing and Networking (CANDAR), Dec.2015.
  27. Akio Nomura,Yu Fujita, Hiroki Matsutani,and Hideharu Amano, “3D Shared Bus Architecture Using Inductive Coupling Interconnect”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep 2015.
  28. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep 2015.
  29. Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi,
    “A Metamorphotic Network-on-Chip for Various Types of Parallel Applications,”
    IEEE International Conference on Application-specific Systems, Architectures and Processors, July, 2015.
  30. Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano,
    “An Optimal Power Supply and Body Bias Voltage for Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET,”
    International Symposium on Low Power Electronics and Design, July, 2015.
  31. Lin-Zhan GUO, MikikoSato, MitaroNamiki: “Energy-Saving Control
    Based on Energy Prediction in KVM Virtualized Environments,” The 2015
    4th ICT International Student Project Conference (ICT-ISPC 2015).
  32. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Staggered Stacking: Connecting Many Small Chips Using ThruChip Interface” CoolChips XVIII, (POSTER) April 13-15 2015. Yokohama, Japan
  33. Akio Nomura, Yu Fujita, Hideharu Amano, “3D bus architecture using indective coupling ThruChip-Interface” CoolChips XVIII, (POSTER) April 13-15 2015. Yokohama, Japan
  34. Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “Ultra Low Power Reconfigurable Accelerator CMA-SOTB-2″ CoolChips XVIII, (BEST POSTER AWARD) April 13-15 2015. Yokohama, Japan
  35. Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano, “A Leakage Current Monitor Circuit Using Silicon on Thin BOX MOSFET for Dynamic Back Gate Bias Control,” CoolChips XVIII, April 13-15 2015. Yokohama, Japan
  36. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel, “Fined-Grained Body Biasing for Frequency Scaling in Advanced SOI Processes,” CoolChips XVIII, April 13-15 2015. Yokohama, Japan
  37. Johannes Maximilian Kuehn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel,” Spatial and Temporal Granularity Limits of Body Biasing in UTBB-FDSOI,” Design Automation & Test in Europe (DATE15), March 9-14. 2015. Grenoble, France
  38. Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, “Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gating,” International Symposium on System-on-Chip 2014, Oct. 2014. (BEST PAPER AWARD)
  39. Y.Fujita, K.Usami, H.Amano, “A thermal management system for building block computing systems,” 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, pp.165-171, Sept. 2014 DOI 10.1109/MCSoC.2014.32 (BEST PAPER AWARD)
  40. R.Yasudo, T.Kagami, H.Amano, Y.Nakase, M.Watanabe, T.Oishi, T.Shimizu, T.Nakamura, “Design of a Low Power NoC Router using Marching Memory Through type,” NOCS2014, 2014.9.17-19, Ferrara, Italy.
  41. T.Katagiri, H.Amano, “A HIGH SPEED DESIGN AND IMPLEMENTATION OF DYNAMICALLY　RECONFIGURABLE PROCESSOR USING 28NM SOI TECHNOLOGY“ The 24th FPL Sept. 2014.
  42. A. Raziz Junaidi, Y. Take and T. Kuroda, “A 352Gb/s Inductive-Coupling DRAM/SoC Interface Using Overlapping Coils with Phase Division Multiplexing and Ultra-Thin Fan-Out Wafer Level Package,“ IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. C36-37, June 2014.
  43. Motoki Wada, Mikiko Sato, Mitaro Namiki: “A Fine Grained Power Management Supported by Just-In-Time Compiler,” IEEE Symposium on Low-Power and High-Speed Chips(CoolChips ) XVII, Yokohama, Japan, 16 Apr., 2014.
  44. Atsushi Koshiba, Jun Tsukamoto, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki: “A Fine-grained Power Gating Control using Leakage Monitor by Linux Process Scheduler,” IEEE Symposium on Low-Power and High-Speed Chips(CoolChips ) XVII, poster 6, Yokohama, Japan, 15 Apr., 2014.
  45. Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano, “Voltage control considering the chip temperature in the three dimensional stacked multiprocessors”, CoolChips XVII (poster) April 2014
  46. Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda and Hiroshi Nakamura, “Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors”, DATE 2014, March 2014
  47. Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu and Hideharu Amano,”Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips”, DATE 2014, March 2014
  48. Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, “Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors”, ASP-DAC 2014. Jan. 2014.
  49. M.Izawa, N.Ozaki, Y.Koizumi, R.Uno, H.Amano, ”A co-processor design of an energy efficient reconfigurable accelerator CMA,” CANDAR 2013, Dec. 2013.
  50. Y.Koizumi, N.Miura, Y.Take, H.Matsutani, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura, ”Demonstration of a Heterogeneous Multi-Core Processor with 3-D Inductive Coupling Links”, FPL2013, Sept. 2013
  51. A.Tsusaka, M.Izawa, R.Uno, H.Amano, ”A Hardware Complete Detection Mechanism for an Energy Efficient Reconfigurable Accelerator CMA,” FPL2013, Sept. 2013
  52. N.Miura, Y.Koizumi, E.Sasaki, Y.Take, H.Matsutani, K.Usami, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura, ”A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface,” (Poster) HOTCHIPS 2013, August 2013.
  53. M.Kudo and K.Usami, “Sleep Control Using Detection of Virtual Ground Voltage for Fine-Grain Power Gating,” ITC-CSCC’13, July 3, 2013
  54. D.Sasaki, H.Matsutani, M.Koibuchi, H.Amano, ”Deadlock-Free Routing Strategy for Stacking 3-D NoCs with Different Topologies,” Proc. of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2013) pp. 88-90, June 2013.

国内学会（招待講演、チュートリアル）

  1. 天野、”ビルディングブロック型計算システムを用いたAIシステム、”ESS2017招待講演　2017.9
  2. 天野、宇佐美、黒田、近藤、竹、中村、並木、松谷、”誘導結合TCIを用いたビルディングブロック型システムのSOTBプロセスによる実装、”、電子情報通信学会ICD研究会招待講演、2016．3
  3. 松谷宏紀　”Open Cell Libraryを用いたデジタルVLSIチップ設計”, 電子情報通信学会ソサイエティ大会チュートリアル、2014．9．24　徳島
  4. 天野英晴　”大学におけるデジタルVLSIチップ開発事例”, 電子情報通信学会ソサイエティ大会チュートリアル、2014．9．24　徳島

国内研究会

  1. 石井潤, 坂本龍一, 近藤正章, “可変データビット幅を持つDNNとそのアクセラレータアーキテクチャの検討,”情報処理学会研究報告 Vol.2017-ARC-227, No.25, 2017年7月.
  2. 濱田 槙亮, 小柴 篤史, 並木 美太郎:SOTBを用いたCPUの省電力OSスケジューラの基本設計,情報処理学会第140回 システムソフトウェアとオペレーティング・システム研究会,Vol.2017-OS-140, No.8, pp.1-8 (2017-05-16)
  3. 前田 剛志, 並木 美太郎: FPGAオフローディングを提供する組込みシステム向けVMMの設計, SWoPP 2017,情報処理学会第141回 システムソフトウェアとオペレーティング・システム研究会,Vol.2017-OS-141, No.10, pp.1-6 (2017-07-26)
  4. 小柴 篤史, 坂本 龍一, 並木 美太郎: オンチップアクセラレータを用いたパイプライン並列処理のためのOS支援機構の検討, SWoPP2017,情報処理学会第141回 システムソフトウェアとオペレーティング・システム研究会,Vol.2017-OS-141,No.21, pp.1-8 (2017-07-27)
  5. 高田遼, 石井潤, 坂本龍一, 近藤正章, 中村宏, 大久保徹以, 小島拓也, 天野英晴,”ディープニューラルネットワーク向けアクセラレータチップの設計と性能評価”, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG2017), 2017年4月.
  6. 林遼, 森下真幸, 高田遼, 坂本龍一, 近藤正章, 中村宏, “ディープラーニング向けアクセラレータアーキテクチャのFPGA実装,” 情報処理学会研究報告 Vol.2016-ARC-222, No.12, 2016年10月
  7. 高田遼, 石川潤, 坂本龍一, 近藤正章, 中村宏, 大久保徹以, 小島拓也, 天野英晴, “スケーラブルなディープラーニング向けアクセラレータチップの設計と評価,” 情報処理学会研究報告 Vol.2016-ARC-223,No.4, 2016年11月.
  8. 佐藤 未来子, 榎本 絵理, 小柴 篤史, 並木 美太郎:細粒度パワーゲーティングを用いたリアルタイムタスク向け最適省電力スケジューリング手法, 情報処理学会研究報告「システムソフトウェアとオペレーティング・システム」, Vol.2016-OS-137, No.9, pp.1-8 (2016-05-31)
  9. 小柴 篤史, 佐藤 未来子, 並木 美太郎:仮想化環境における指数平滑化法を用いたVMの性能予測に基づくDVFS制御のKVM上での評価と分析, 情報処理学会研究報告「システムソフトウェアとオペレーティング・システム」Vol.2016-OS-138, No.3, pp.1-9 (2016-08-08)
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