Researchers

• Shibaura Institute of TechnologyCircuit Technologies, Low Power Techniques 
• Keio University Kuroda Lab. Through Chip Interface with Inductive Coupling Links
• University of Tokyo, Kondo Lab. Building Block Architecture, Compiler Techniques
• University of Tokyo, Nakamura Lab. Building Block Architecture, Fault Tolerant Technologies
• Tokyo University of Agriculture and Technology Building Block OS
• Keio University, Matsutani Lab. Network on Chips