declare fadder {
	input a, b, ci ;
	output s, co ;
	instrin enable ;
	instr_arg enable(a, b, ci);
}
module addsub4{
input ina<4>, inb<4>, sub ;
output sumdiff<4> ;
instrin enable ;
sel_v c0,c1,c2,st3,st2,st1,st0, bb<4> ;
fadder fa0, fa1, fa2, fa3 ;
instruct enable par {
	alt { sub: bb = ^inb ;
		else: bb = inb ; }
	st0 = fa0.enable(ina<0>, bb<0>, sub).s; c0 = fa0.co;
	st1 = fa1.enable(ina<1>, bb<1>, c0).s; c1 = fa1.co;
	st2 = fa2.enable(ina<2>, bb<2>, c1).s; c2 = fa2.co;
	st3 = fa3.enable(ina<3>, bb<3>, c2).s;
	sumdiff = st3||st2||st1||st0;
}
}
/**************************/
/*	1bit Full adder       */
/**************************/
module fadder {
    input a, b, ci ;
    output s, co ;
    instrin enable ;
    instruct enable par {
    s = (a & ^b & ^ci)|(^a & b & ^ci)|(^a & ^b & ci)|(a & b & ci) ;
	co = (a & b )|(b & ci)|(a & ci) ;
	}
}