■verilog ネットリストの読み込み
レイアウトを行うネットリストの読み込み
auVerilogToCell で行う
●スクリプト
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./scripts/verilog_to_cell.tcl
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auVerilogToCell
formDefault verilog_to_cell
setFormField verilog_to_cell library_name ${libName}
setFormField verilog_to_cell verilog_file_name ${srcDir}/${srcName}.vnet
setFormField verilog_to_cell output_cell_name ${celName}
setFormField verilog_to_cell top_module_name ${designName}
setFormField verilog_to_cell tech_file_name ${techFileName}
setFormField verilog_to_cell bus_naming_style \[%d\]
setFormField verilog_to_cell net_name_for_1'b0 $vssNet
setFormField verilog_to_cell net_name_for_1'b1 $vddNet
setFormField verilog_to_cell set_case_sensitive 1
setFormField verilog_to_cell open_library_and_cell_when_done 1
formButton verilog_to_cell globalNetOptions
setFormField verilog_to_cell net_name $vddNet
setFormField verilog_to_cell port_pattern VDD
formButton verilog_to_cell apply
setFormField verilog_to_cell net_name $vssNet
setFormField verilog_to_cell port_pattern VSS
formButton verilog_to_cell apply
formButton verilog_to_cell refLibOptions
foreach lib [concat $common_libs $additional_libs] {
setFormField verilog_to_cell reference_library ${lib}
formButton verilog_to_cell add
}
formOK verilog_to_cell