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2024

受賞

RECONF研究会　若手講演賞

  • Wei Kai jie , 天野 英晴, 庭瀬稜平, 三好健文, 山口佳樹”FPGAを用いた状態ベクトル型量子シミュレータ用データ圧縮技術の開発”, (RECONF研究発表会 202④年1月)

2023

受賞

RECONF研究会　若手講演賞

  • 小島　拓也, 矢内 洋祐 , 天野 英晴, 奥原　颯, 久我 守弘, 飯田 全広, “FPGAとRISC-Vプロセッサを搭載したSoC向けHW/SW設計フローと実機評価”, (RECONF研究発表会 2023年９月)

SLDM研究会優秀発表賞・セッション特別賞

  • 福嶋泰優, 飯塚健介, 天野英晴, “マルチFPGA上でのVision Transformerの並列実装”, (第201回SLDM研究発表会 2023年1月)

Journal

  1. Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, “A Scalable Body Bias Optimization Method Towards Low-Power CGRAs”, IEEE Micro, Vol. 43, no. 1, pp. 49-57, Jan.-Feb. 2023. DOI: 10.1109/MM.2022.3226739. [IEEE Xplore]
  2. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of CNN on Multi-FPGA Cluster”, IEICE Transactions on Information and Systems,Volume E106-D, No.7, Pages 1198-1208, 2023.
  3. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 4, pp. 532-542, April 2023, doi: 10.1109/TVLSI.2023.3237794. [IEEE Xplore]
  4. Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano, “Power Analysis and Power Modeling of Directly-connected FPGA Clusters”, IEICE Transactions (accepted).
  5. Hideto Kayashima, Hideharu Amano, “TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface”, Journal of Low Power Electronics and Applications, vol. 13, no.3, Aug. 2023. DOI: 10.3390/jlpea13030048.
  6. Ullah IMDAD, Akram BEN AHMED, Kazuei HIRONAKA, Kensuke Iizuka, Hideharu Amano, “A multi-FPGA implementation of FM-index based Genomic Pattern
    Search,” IEICE Trans. on Fundamentals, (accepted)
  7. K.Usami, H.Yokoyama, A.Kamei, H.Amano, K.Suzuki, K.Hiraga, K.Bessho, “Optimized Two-Step Store Control for MTJ-based Non-Volatile Flip-FLops to Minimize Store Energy under Process and Temperature Variations,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (Accepted)

国内研究会

  1. 福嶋泰優, 飯塚健介, 天野英晴, “マルチFPGA上でのVision Transformerの並列実装”, 研究報告システムとLSIの設計技術（SLDM）,2023-SLDM-201(6),1-10 (2023-01-16) , 2188-8639, 2023年1月.
  2. 飯塚健介，亀井愛佳，弘中和衛，天野英晴, “FPGAクラスタの消費電力モデルの提案”, 信学技報, vol. 122, no. 451, CPSY2022-45, pp. 66-71, 2023年3月.
  3. 茅島秀人，亀井愛佳，小島拓也，天野英晴，”誘導結合無線通信インタフェースにおけるバスアービトレーション方法の検討”, 信学技報, vol. 123, no. 145, CPSY2023-17, pp. 55-60, 2023年8月
  4. 亀井 愛佳, 天野 英晴, 小島 拓也, 宇佐美 公良, 平賀 啓三, 鈴木 健太, 別所 和宏, “不揮発性 FF のエネルギーモデルを用いた間欠動作アプリケーションのエネルギー最小化”, DA シンポジウム 2023 論文集, pp. 235-242, 2023年8月.

国際会議

  1. Ziquan Qin, Kaijie Wei, Hideharu Amano and Kazuhiro Nakadai, “Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board,” 2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2023, pp.
  2. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “Verify-and-Retryable MTJ-based Nonvolatile Flip-Flops on Multi-Context CGRA,” The 31st IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) Demo Night, May. 2023.
  3. T.Okuyama, H.Amano, K.Ohkoda, M.Aono, “Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing,” Proc. on HEART23, ACM, Jun.2023.
  4. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster”, Proceedings of 11th International Symposium on Computing and Networking (CANDAR 2023), Matsue, Japan, November 2023
  5. R.Niwase, H.Hasegawa, Y.Yamaguchi, K.Wei, H.Amano, “A cost/power efficient storage system with directly connected FPGA and SATA disks,” Proc. of McSoC 2023, Dec. 2023
  6. Takumi Inage, Kensuke Iizuka, Hideharu Amano, “Board Allocation Algorithm for the Resource Management System of FiC”, Proceedings of 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), December, 2023.



2022

受賞

電情報処理学会システム・アーキテクチャ研究会若手奨励賞

  • 四釜快弥, 鯉渕道紘, 天野英晴 “コヒーレンス制御機構を利用した検知困難なハードウェア・トロイの木馬による攻撃” (CPSY 2022年1月)

山下記念研究賞

  • 亀井 愛佳, “不揮発性FFを用いたCGRA設計探索のためのばらつきを考慮したMTJへの書き込みエネルギー推定モデルの提案” (ETNET 2022年3月)

SLDM研究会優秀発表賞

  • 亀井 愛佳, “不揮発性FFを用いたCGRA設計探索のためのばらつきを考慮したMTJへの書き込みエネルギー推定モデルの提案” (ETNET 2022年3月)

IEEE CEDA AJJC Academic Research Award

  • Aika Kamei, “A Variation-Aware MTJ Store Energy Estimation Model for Design Exploration of CGRA with Nonvolatile Flip-Flops” (ETNET Mar., 2022)

HEART 2022 Best Paper Award

  • Kaijie Wei, Yuki Kuno, Masatoshi Arai, and Hideharu Amano, RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. 2022 International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2022), June, 2022

電子情報通信学会コンピュータシステム研究会優秀若手発表賞

  • 矢内洋祐, 小島拓也, 奥原颯, 飯田全広, 天野英晴, “RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの予備評価” (CPSY 2022年7月)

IEEE Computer Society Japan Chapter Young Author Award 2022

  • Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems.

Journal

  1. T.Shimizu, K.Ito, K.Iizuka, K.Hironaka, H.Amano, “The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System,” IEICE Transactions on Inf. & Syst., Accepted.
  2. 弘中、稲毛、飯塚、伊藤、天野、”Multi-access Edge Computing 用 FPGA システム M-KUBOS クラスタの開発,” 電子情報通信学会論文誌　D分冊　2022、　採録決定
  3. Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai, “Weight Least Square Filter for Improving the Quality of Depth Map on FPGA”, The International Journal of Networking and Computing (IJNC), Accepted.
  4. N. Niwa, H. Amano, and M. Koibuchi, “Boosting the performance of interconnection networks by selective data compression,” IEICE Transactions on Information and Systems, vol.E105-D, no.12, 2022., Accepted.
  5. K. Wei, Y.Kuno, M.Arai, and H.Amano, “RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability”, IEICE Transactions on Information and Systems,Volume E106-D, Issue 3, Pages 337-348, 2022 Accepted

国際会議

  1. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings,” PDP 2022, Jan. 2022.
  2. Hajime Takishita, Yuan He, Masaaki Kondo, Hideharu Amano, “Accelerating Graph-Based SLAM on an M-KUBOS Board towards Multi-access Edge Computing”, COOLCHIPS25(Poster), April 2022
  3. Shigeyuki Takano and Hideharu Amano, “Study of General-Purpose CGRA Architecture”, COOLCHIPS25(Poster), April 2022
  4. Hou Zhongyang, Wei Kaijie, Hideharu Amano, Kazuhiro Nakadai, “Implementation of HARK Sound source localization by M-KUBOS“, COOLCHIPS25(Poster), April 2022
  5. Huang Pengyu, Wei Kaijie, Hideharu Amano, Kaori Ohkoda, Masashi Aono, “Multi-FPGA Implementation of Distributed Computing System for Solving the Transportation Optimization Problem“, COOLCHIPS25(Poster), April 2022
  6. Qin Ziquan, Wei Kaijie, Hideharu Amano, Kazuhiro Nakadai, “An implementation of Geometric High-order Dicorrelation-based Source Separation on an FPGA board”, COOLCHIPS25(Poster), April 2022
  7. Zhou Yuqing, Naoya Niwa, Hideharu Amano, “Distant-aware Compression for interconnection network of many-core systems”, COOLCHIPS25(Poster), April 2022
  8. Chen Yuchen, Wei Kaijie, Hideharu Amano, “An implementation of image filters on an FPGA board”, COOLCHIPS25(Poster), April 2022
  9. Shao Ningyu, Hiroaki Suzuki, Hideharu Amano, Wataru Takahashi, Kazutoshi Wakabayashi, “A CNN implementation on a multi-FPGA system with system-C description”, COOLCHIPS25(Poster), April 2022
  10. Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, and Hideharu Amano, “Power Analysis of Directly-connected FPGA Clusters,” 2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2022, pp. 1-6, doi: 10.1109/COOLCHIPS54332.2022.9772675.
  11. Kaijie Wei, Yuki Kuno, Masatoshi Arai, and Hideharu Amano, RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. 2022 International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2022), June, 2022
  12. Shigeyuki Takano and Hideharu Amano, “Reconfiguration Cost for Reconfigurable Computing Architectures”, IEEE/ACIS International Fall Virtual Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, July 2022 (accepted)
  13. Yuchen Chen, Kaijie Wei, Hiroaki Nishi and Hideharu Amano, “An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board”, Proceedings of 10th International Symposium on Computing and Networking (CANDAR 2022), Himeji, Japan, November 2022
  14. Pengyu Huang, Kaijie Wei, Hideharu Amano and Masashi Aono, “Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory”, Proceedings of 13th International Workshop on Advances in Networking and Computing (WANC 2022), Himeji, Japan, November 2022
  15. Zhongyang Hou, Kaijie Wei, Hideharu Amano and Kazuhiro Nakadai, “An FPGA Implementation of HARK Sound source localization”, Proceedings of 5th Sustainable Computing Systems Workshop (SUSCW2022), Himeji, Japan, November 2022
  16. Aoi Hiruma, Kensuke Iizuka and Hideharu Amano, “Toward a training of CNNs on a multi-FPGA system”, Proceedings of 5th Sustainable Computing Systems Workshop (SUSCW2022), Himeji, Japan, November 2022

国内研究会

  1. ウェイ カイジ, 久野祐輝, 新井正敏, 天野英晴, “FPGAを用いたリアルタイムステレオマッチングシステムの構築”, 信学技報, vol.121, no.344, RECONF2021-73, pp. 90-95, 2022年1月.
  2. 四釜快弥, 鯉渕道紘, 天野英晴, “コヒーレンス制御機構を利用した検知困難なハードウェア・トロイの木馬による攻撃”, 信学技報, vol. 121, no. 343, CPSY2021-44, pp. 148-153, 2022年1月.
  3. 瀧下創,和遠,近藤正章,天野英晴, “Graph-Based SLAMのFPGAによる高速化の検討”,研究報告組込みシステム（EMB）, 2022-EMB-59(52),1-6 (2022-03-03) , 2188-868X （ETNet）,  2022年3月
  4. 亀井 愛佳, 天野 英晴, 小島 拓也, 横山 大輝, 宮内 陽里, 宇佐美 公良, 平賀 啓三, 鈴木 健太, 別所 和宏, “不揮発性FFを用いたCGRA設計探索のためのばらつきを考慮したMTJへの書き込みエネルギー推定モデルの提案”, 情報処理学会研究報告, Vol.2022-SLDM-198 No.26, 2022年3月.
  5. 高野茂幸, 天野英晴, “汎用粗粒度再構成可能アーキテクチャの検討”, 研究報告システム・アーキテクチャ（ARC）, 2022-ARC-248(10),1-7 (2022-03-03) , 2188-8574 （ETNet）,  2022年3月
  6. 飯塚健介, 高木春奈, 亀井愛佳, 弘中和衛, 天野英晴, “FPGAクラスタのための電力測定ツールの導入と消費電力の分析”, 信学技報, vol. 122, no. 60, RECONF2022-18, pp. 80-85, 2022年6月
  7. 矢内洋祐, 小島拓也, 奥原颯, 飯田全広, 天野英晴, “RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの予備評価”, 信学技報, vol. 122, no. 133, CPSY2022-8, pp. 41-46, 2022年7月.
  8. 邵　寧禹, 鈴木裕章, 高橋　渡, 若林一敏, 天野英晴, “System-C 記述に基づくマルチFPGAシステム上へのCNNのシミュレーション”, 信学技報, vol. 122, no. 174, RECONF2022-28, pp.7-12, 2022年9月
  9. 陳　宇晨, ウェイ カイジ, 西　宏章, 天野 英晴, “動きベクトル検出用3D画像フィルタのFPGAへの実装”, 信学技報, vol. 122, no. 174, RECONF2022-28, pp.13-14, 2022年9月
  10. 周　宇擎, 丹羽 直也, 天野 英晴, “距離に依存して圧縮を選択する転送方式 DA selective compression の提案”, 信学技報, vol. 122, no. 174, RECONF2022-28, pp.14-15, 2022年9月
  11. 黄　鵬宇, ウェイ カイジ, 天野 英晴, 青野 真士, “AmoebaTopのマルチFPGA上での実装”, 信学技報, vol. 122, no. 174, RECONF2022-28, pp.17-18, 2022年9月
  12. 侯　中陽, ウェイ カイジ, 天野 英晴, 中臺 一博, “音源位置特定処理のFPGAボードへのオフロード”, 信学技報, vol. 122, no. 174, RECONF2022-28, pp.19-20, 2022年9月
  13. 覃　梓権, ウェイ カイジ, 天野 英晴, 中臺 一博, “音源分離処理のFPGA上での実装”, 信学技報, vol. 122, no. 174, RECONF2022-28, pp.21-22, 2022年9月



2021

受賞

SLDM優秀論文賞

  • 福嶋泰優, “PYNQクラスタ上でのResNetの並列実装”, (ETNET 2021年3月)

SLDM優秀発表賞

  • 亀井愛佳, “不揮発性FFを用いたマルチコンテキストCGRA”, (デザインガイア 2021年10月)

MCSoC 2021 Best Paper Award

  • Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops”

CANDAR Outstanding Paper Award

  • Naoya Niwa, Hideharu Amano, Michihiro Koibuchi, “Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.

第37回電気通信普及財団賞　テレコムシステム技術学生賞

  • Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems.

Journal

  1. 小島拓也, 池添赳治, 天野英晴, “3次元積層SiPを用いたマルチコアシステムのためのサイクルアキュレートシミュレータCubeSimの開発”, 電子情報通信学会論文誌D, Vol.J104-D,No.04,pp.228-241,Apr. 2021. DOI:10.14923/transinfj.2020PDP0046[Open access]
  2. Takeharu Ikezoe, Takuya Kojima, Hideharu Amano, “Recovering faulty Non-volatile Flip Flops for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Electronics. Vol.E104-C, No.6, pp.215-225, Jun. 2021. DOI:10.1587/transele.2020LHP0002. [Open access]
  3. Ryota Yasudo, Jose Gabriel Figueiredo Continho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, and Tobias Becker, “Analytical Performance Estimation for Large-scale Reconfigurable Dataflow Platforms,” ACM Transactions on Reconfigurable Technology and Systems. (Accepted)
  4. Kazuei HIRONAKA,Kensuke IIZUKA,Miho YAMAKURA,Akram BEN AHMED,and Hideharu AMANO, “Remotedynamic reconfiguration of a multi-FPGA system FiC (Flow-in-Cloud)”, IEICE Trans. Information and Systems,Vol.E104-D,No.8,pp.-,Aug. 2021. (To appear)
  5. Kaijie Wei, Koki Honda and Hideharu Amano “An implementation methodology for Neural Network on a Low-end FPGA Board”, International Journal of Networking and Computing(IJNC). Vol.11, No.2, pp.-, July. 2021. (Accepted)
  6. Koki honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano “CLAHE implementation and evaluation on a low-end FPGA board by high-level synthesis”, IEICE Trans. Information and Systems, Vol.E104-D,No.12,pp.-,Dec. 2021(Accepted)
  7. Miho Yamakura, Ryousei Takano, Akram Ben Ahmed, Midori Sugaya, Hideharu Amano “A Multi-tenant Resource Management System for Multi-FPGA Systems”, IEICE Trans. Information and Systems, Vol.E104-D,No.12,pp.-,Dec. 2021(Accepted)
  8. Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano “Improving the Performance of Circuit-switched Interconnection Network for a Multi-FPGA System”, IEICE Trans. Information and Systems, Vol.E104-D,No.12,pp.-,Dec. 2021(Accepted)
  9. Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems. [IEEE Xplore]

国際会議

  1. Hideto Kayashima and Hideharu Amano, “TCI Tester: Tester for Through Chip Interface”, The University Design Contest of The 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021), pp.107-108, January 2021
  2. Naoya Niwa, Yoshiya Shikama, Hideharu Amano, and Michihiro Koibuchi, “A Case for Low-Latency Network-on-Chip using Compression Routers”, Proc. of the 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2021), 10-12 Mar. 2021.
  3. Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto and Michihiro Koibuchi, “Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths”, Proc. of the 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2021), 10-12 Mar. 2021.
  4. Ohwada Ayaka, Takuya Kojima, and Hideharu Amano, “MENTAI: A Fully Automated CGRA Application Development Environment that Supports Hardware/Software Co-design”, Synthesis And System Integration of Mixed Information technologies(SASIMI2021), Mar. 2021.
  5. Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano, “Hybrid Network of Packet Switching and STDM in a Multi-FPGA System”, COOLCHIPS24, April 2021
  6. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of CNN on PYNQ Cluster”, COOLCHIPS24, April 2021
  7. Yuki Kameyama, Yoshiya Shikama, Naoya Niwa, Michihiro Koibuchi, Hideharu Amano, “Optimal placement of coherence directories using memory networks”, COOLCHIPS24, April 2021
  8. Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano, “Software management system of the PYNQ cluster”, COOLCHIPS24, April 2021
  9. Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano, “Multi-FPGA board design using CyberWorkBench, a high-level synthesis tool”, COOLCHIPS24, April 2021
  10. Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano, “A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool”, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), June 2021
  11. Hideto Kayashima and Hideharu Amano, “Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.
  12. Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki and Hideharu Amano, “M-KUBOS/PYNQ Cluster for multi-access edge computing”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.
  13. Naoya Niwa, Hideharu Amano, Michihiro Koibuchi, “Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.
  14. Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno and Masatoshi Arai, “Weight Least Square Filter for Improving the Quality of Depth Map on FPGA,” 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW), 2021.
  15. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of CNN on Multi-FPGA Cluster”, The IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2021), December, 2021.
  16. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops”, The IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2021), December, 2021.
  17. Y.Yan, H.Amano, M.Aono, K.Ohkoda, S.Fukuda, K.Saito, S.Kasai, “Resource-saving FPGA Implementation of the Satisfiability Program Solver: AmoebaSATslim,” ICFPT 2021, Dec.2021

国内研究会

  1. 福嶋泰優, 飯塚健介, 天野英晴, ”PYNQクラスタ上でのResNetの並列実装”, 研究報告システムとLSIの設計技術（SLDM）,2021-SLDM-194(43),1-8 (2021-03-18) , 2188-8639
  2. 鈴木裕章, 高橋渡, 若林一敏, 天野英晴, “高位合成ツールCyberWorkBenchを用いたマルチFPGAボード設計”, 信学技報, vol. 120, no. 339, RECONF2020-79, pp. 119-124, 2021年1月.
  3. 稲毛琢己, 弘中和衛, 飯塚健介, 天野英晴, “M-KUBOSを用いたPYNQクラスタの構築”, 信学技報, vol. 120, no. 338, CPSY2020-41, pp. 107-112, 2021年1月.
  4. 亀山祐己, 四釜快弥, 丹羽直也, 鯉渕道紘, 天野英晴, “メモリネットワークを用いたコヒーレンスディレクトリの最適配置”, CPSY研究会, 2021年3月.
  5. 亀井愛佳, 小島拓也, 天野英晴, 横山大輝, 宮内陽里, 宇佐美公良, 平賀啓三, 鈴木健太, 別所和宏, “不揮発性FFを用いたマルチコンテキストCGRA”, 信学技報, vol. 121, no. 277, VLD2021-20, pp. 19-24, 2021年12月.



2020

受賞

電子情報通信学会コンピュータシステム研究会優秀若手発表賞

  • 大和田彩夏 “LLVMを用いたCGRA向けソフトウェア開発環境の構築と評価” (ETNET 2020年2月)

CANDAR SUSCW Best Paper Award

  • Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke IIzuka, Hideharu Amano, “Horizontal division of deep learning applications with all-to-all communication on a multiFPGA system”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020

Journal

  1. Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano Hideharu, Rodney Van Meter “Extracting Success from IBM’s 20-Qubit Machines Using Error-Aware Compilation”,Journal on Emerging Technologies in Computing Systems, Vol.16, Issue 3, July 2020.
  2. Ryuta Kawano, Tyota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    “Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks,” IEICE Trans on Inf&Tech,Vol.E103-D,No.12,pp.-,Dec. 2020
  3. Yuxi Sun, Hideharu Amano, “FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks”, IEICE Trans. on Inf&Tech,Vol.E103-D,No.12,pp.-,Dec. 2020
  4. Carlos C. Cortes Torres, Ryota Yasudo and Hideharu Amano, “Body Bias Optimization for Real-Time Systems”, Journal of Low Power Electronics and Applications, Vol.10,No.1,Feb.2020. DOI:10.3390/jlpea10010008.
  5. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “A Generalized Theory based on the Turn Model for Deadlock-Free Irregular Networks”, IEICE Transactions on Information and Systems, Vol.E103-D, No.01, pp.101–110, Jan 2020.
  6. Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano, “GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse Grained Reconfigurable Architectures”, IEEE Transactions on Very Large Scale Integration Systems (VLSI), Vol. 28, no. 11, pp.2383-2396, Nov 2020.[IEEE Xplore][Tool available at Github]
  7. Ryota Yasudo, Hiroki Matsutani, Koji Nakano, Hideharu Amano, Michihiro Koibuchi, “Designing Low-Diameter Interconnection Networks with Multi-ported Host-Switch Graphs” The Concurrency and Computation: Practice and Experience. (Accepted)

国際会議

  1. Hideharu Amano, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Yugo Yamauchi, M.M.Imdad Ullah, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Tomotaka Shimizu, Kohei Ito, “Flow-in-Cloud: a Scalable multi-FPGA system for HPC”, HiPEAC2020 EuroEXA workshop, Jan 2020, Bologna
  2. Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano, “Implementation of a Packet-Switching Router on a Multi-FPGA System”, COOLCHIPS23, April 2020
  3. Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano, “Implementation of an Application Utilized Multi-Switch on a Multi-FPGA System”, COOLCHIPS23, April 2020
  4. Yoshiya Shikama, Kawano Ryuta, Akram Ben Ahmed, Hiroki Matsutani, Michiciro Koibuchi, Hideharu Amano, “Low-Latency Memory Packet Network Using Bypassing”, COOLCHIPS23, April 2020
  5. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “Compiler Framework for Spatial Mapping CGRA using LLVM”, COOLCHIPS23, April 2020 [poster] [slide]
  6. Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano, “A Method of Partitioning Convolutional Layer to Multiple FPGAs”, 17th International SoC Design Conference (ISOCC), pp.25-pp.26, Oct. 2020.
  7. Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke IIzuka, Hideharu Amano, “Horizontal division of deep learning applications with all-to-all communication on a multiFPGA system”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020
  8. Kohei Ito, Kensuke IIzuka,Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano, “Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020.
  9. Kaijie Wei, Koki Honda and Hideharu Amano, “An implementation methodology for Neural Network on a Low-end FPGA Board”, 2020 Eighth International Symposium on Computing and Networking (CANDAR), November, 2020.
  10. Manfred Orsztynowicz, Kenichi Kubota, Hideharu Amano and Takaaki Miyajima, “Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA”, 2020 Eighth International Symposium on Computing and Networking (CANDAR), November, 2020.
  11. Koki Honda, Wei Kaijie, Masatoshi Arai and Hideharu Amano. “CLAHE implementation on a low-end FPGA board by high-level synthesis”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020.

国内研究会

  1. 河野 隆太, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, “最小直径ネットワークトポロジのラック配置最適化”, 電子情報通信学会技術研究報告, CPSY2019-56, Vol.119, No.372, pp.25–30, Jan 2020. [Paper] [Slide] [GitHub]
  2. 伊藤光平, 飯塚健介, 山内脩吾, 弘中和衛, 胡曜, 鯉渕道紘, 天野英晴, “マルチFPGAにおける複数スイッチを使用した際の性能評価”, 信学技報, vol. 119, no. 372, CPSY2019-58, pp. 37-42, 2020年1月.
  3. 清水智貴, 伊藤光平, 飯塚健介, 山内脩吾, 弘中和衛, 天野英晴, “ルータのマルチFPGAシステムへの実装と性能評価”, 信学技報, vol. 119, no. 372, CPSY2019-57, pp. 31-36, 2020年1月.
  4. 本田紘規,ウェイ カイジ,新井正敏,天野英晴, “CLAHEの低価格Zynqボードを用いた高位合成による実装”, 信学技報, vol. 119, no. 373, RECONF2019-44, pp. 1-5, 2020年1月.
  5. 四釜快弥, 河野隆太, Akram Ben Ahmed, 松谷宏紀, 鯉渕道紘, 天野英晴, “バイパシングによる低遅延メモリパケットネットワーク”, 信学技報, vol. 119, no. 428, CPSY2019-93, pp. 7-12, 2020年2月.
  6. 小島拓也, 池添赳治, 天野英晴, “3次元積層型ヘテロジニアスプロセッサのためのシミュレータ開発とその応用”, 信学技報, vol. 119, no. 428, CPSY2019-103, pp. 93-98, 2020年2月.
  7. 大和田彩夏, 小島拓也, 天野英晴, “LLVMを用いたCGRA向けソフトウェア開発環境の構築と評価”, 信学技報, vol. 119, no. 428, CPSY2019-109, pp. 145-150, 2020年2月.
  8. 河野 隆太, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, “低直径ネットワークトポロジのラック配置最適化”, 情報処理学会第82 回全国大会講演論文集, pp.1:33–1:34, Mar 2020 [Slide].
  9. 弘中和衛, 山倉美穂, 天野英晴, “マルチFPGAシステムにおける部分再構成の実際”, 信学技報, vol. 120, no. 36, RECONF2020-16, pp. 85-90, 2020年5月.
  10. 大和田彩夏, 小島拓也, 天野英晴, “CGRAアプリケーションのIPベース設計環境の提案”, 信学技報, vol. 120, no. 121, CPSY2020-6, pp. 37-42, 2020年7月.
  11. 小島拓也, 大和田彩夏, 天野英晴, “深層学習を用いたCGRAの効率的なアプリケーションマッピング手法”, 信学技報, vol. 120, no. 121, CPSY2020-7, pp. 43-48, 2020年7月.
  12. 天野英晴, 弘中和衛, 飯塚健介, “M-KUBOSボードを用いた次世代FiC”, 信学技報, vol. 120, no. 121, CPSY2020-9, pp. 55-60, 2020年7月.
  13. 茅島秀人, 天野英晴, 四手井綱章, “誘導結合無線通信インタフェース搭載チップにおける抵抗分布解析”, 信学技報, vol. 120, no. 234, VLD2020-19, pp. 48-53, 2020年11月.



2019

受賞

COOL Chips 22 Featured Poster Award

  • Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano, ”Partial Reconfiguration Technique for a Multi-board FPGA System FiCSW”

MCSoC 2019 Best Paper Award

  • Hayate Okuhara, Ryosuke Kazami, and Hideharu Amano, “A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration”

山下記念研究賞

  • 河野 隆太, “ルーティングアルゴリズムによる通信帯域の測定と理解”, ARC-232, (SWoPP’18), 2018年7月.

IEEE CEDA AJJC Design Gaia Best Poster Award 2019

  • Takuya Kojima, “Evaluation of A Novel Application Mapping Framework for CGRAs”

Journal

  1. Takuya Kojima and Hideharu Amano, “A Fine-Grained Multicasting of Configuration data for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E102-D,No.7, pp.1247-1256,Jul. 2019. DOI:10.1587/transinf.2018EDP7336.

国際会議

  1. Yugo Yamauchi, Kazusa Musha, Hideharu Amano, “Implementing LSTM on the multi-FPGA sytem: Flow-in-Cloud.”, COOLCHIPS22, April 2019.
  2. Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano, ”Real Chip Performance Evaluation of Inductive Coupling TCI IP”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  3. Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano, ”Partial Reconfiguration Technique for a Multi-board FPGA System FiCSW”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  4. Koki Honda, Wei Kaijie, Hideharu Amano, ”The Framework for Image Processing Aiming to Autonomous Car Using FPGA”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  5. Yasuaki Okamoto, Hideharu Amano, ”Implementation of ART algorithm with Xilinx SDAccel”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  6. Aoi Hiruma, Yugo Yamauchi, Kazusa Musha, Hideharu Amano, ”Implementation of Training Phase of Convolutional Neural Networks on a Multi-FPGA system”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  7. Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, and Hideharu Amano, “An ARM-based heterogeneous FPGA accelerator for hall thruster simulation”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2019), June, 2019, Nagasaki, Japan.
  8. Yuxi Sun, Akram Ben Ahmed, and Hideharu Amano, “Acceleration of deep recurrent neural networks with an FPGA cluster”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2019), June, 2019, Nagasaki, Japan.
  9. Yamakura Miho, Hironaka Kazuei, Azegami Keita, Musha Kazusa, and Amano Hideharu, “The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2019), June, 2019, Nagasaki, Japan.
  10. Takuya Kojima and Hideharu Amano, “Refinements in Data Manipulation Method for Coarse Grained Reconfiguration Architectures”, 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2019), York, United Kingdom, July, 2019.
  11. Kazuei Hironaka, Akram Ben Ahmed, and Hideharu Amano, “Multi-FPGA Management on Flow-in-Cloud Prototype System”, 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2019), July, Toyama, Japan.
  12. Takuya Kojima, Naoki Ando, Yusuke Matsushita and Hideharu Amano, “Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA”, 29th International Conference on Field Programmable Logic and Applications (FPL), pp. 411-412, Barcelona, Spain, September, 2019. (Demo Paper)
  13. Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M M Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, and Hideharu Amano, “Demonstration of Flow-in-Cloud: A multi-FPGA system”, 29th International Conference on Field Programmable Logic and Applications (FPL), pp. 417-418, Barcelona, Spain, September, 2019. (Demo Paper)
  14. Hayate Okuhara, Ryosuke Kazami, and Hideharu Amano, “A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.32-37, Singapore, October, 2019.
  15. Koki Honda, Kaijie Wei, Hideharu Amano, “FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.53-60, Singapore, October, 2019.
  16. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo and Mitaro Namiki, “A Preliminary Evaluation of Buiding Block Computing Systems”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.312-319, Singapore, October, 2019.
  17. Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuch, Yao Hu, Hideharu Amano, “A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.328-333, Singapore, October, 2019.
  18. Ryohei Tomura, Takuya Kojima, and Hideharu Amano, “A Real chip evaluation of a CNN accelerator SNACC”, Synthesis And System Integration of Mixed Information technologies(SASIMI2019), Tainan, Taiwan, October, 2019.
  19. Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano, ”Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process”, 2019 Seventh International Symposium on Computing and Networking Workshop (CANDARW), Nagasaki, Japan, November, 2019.
  20. Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, “Deadlock-Free Layered Routing for Infiniband Networks”, Proc. of the 7th International Symposium on Computing and Networking Workshops (CANDARW’19), pp.84–90, Nov 2019. [Paper] [Slide]
  21. Takeharu Ikezoe, Takuya Kojima and Hideharu Amano, “A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory,” 2019 International Conference on Field-Programmable Technology (ICFPT), Tianjin, China, 2019, pp. 81-89.

国内研究会

  1. 山倉美穂, 畔上佳太, 武者 千嵯, 天野英晴, “FiCSW上での部分再構成の評価”, 信学技報, vol. 118, no. 431, CPSY2018-92, pp. 59-64, 2019年1月.
  2. 本田紘規, ウェイカイジ,天野英晴, “自動運転の実現に向けた画像処理アルゴリズムのFPGAによる実装”, 信学技報, vol.118, no. 432, RECONF2018-54, pp. 49-53, 2019年1月.
  3. 丹羽直也, 平澤将一, 鯉渕道紘, 天野英晴, “Approximate 相互結合網を用いた巡回セールスマン問題の並列蟻コロニー最適化による解法の高速化”, 信学技報, vol. 118, no. 514, CPSY2018-110, pp. 193-198, 2019年3月.
  4. 比留間葵, 山内脩吾, 武者千嵯, 工藤知宏, 天野英晴, “マルチFPGAにおける畳み込みニューラルネットワークの実装手法”, 信学技報, vol. 118, no. 514, CPSY2018-116, pp. 259-264, 2019年3月.
  5. 茅島秀人, 小島拓也, 奥原颯, 四手井綱章, 天野英晴, “誘導結合TCI IPの実チップにおける性能測定”, LSIとシステムのワークショップ2019, ポスターセッション, no.26, 2019年5月.
  6. 天野英晴, 茅島秀人, 四手井綱章, 小島拓也, “ルネサスSOTB65nm用Through Chip Interface IPの実機評価”, 信学技報, vol. 119, no. 25, VLD2019-5, pp. 31-36, 2019年5月.
  7. 岡本泰明, 天野英晴, “Xilinx SDAccelによるART法の高速化”, 信学技報, vol. 119, no. 76, CPSY2019-14, pp. 117-121, 2019年6月.
  8. 風見亮佑, 天野英晴, “マルチエージェント SLAMの実装”, 信学技報, vol. 119, no. 76, CPSY2019-15, pp. 123-126, 2019年6月.
  9. 天野英晴, 茅島秀人, 小島拓也, 坂本龍一, 近藤正章, 並木美太郎, “ビルディングブロック型積層システムの性能評価”, 信学技報, vol. 119, no. 147, CPSY2019-17, pp. 1-6, 2019年7月.
  10. 小島拓也, 天野英晴, “粗粒度再構成可能アーキテクチャCMAにおけるメモリバンクアクセスの改良”, 信学技報, vol. 119, no. 147, CPSY2019-22, pp. 85-90, 2019年7月.
  11. 飯塚健介, 天野英晴, “AlexNetのマルチFPGAシステムへの分割検討と実装”, 信学技報, vol. 119, no. 147, CPSY2019-23, pp. 91-95, 2019年7月.
  12. 河野隆太, 松谷宏紀, 鯉渕道紘, 天野英晴, “Infinibandネットワークでのデッドロックフリーな階層型ルーティング”, 信学技報, vol. 119, no. 147, CPSY2019-28, pp. 147-152, 2019年7月.
  13. 丹羽直也, 鯉渕道紘, 天野英晴, “BigDataBenchによるApproximate Networkの性能評価”, 信学技報, vol. 119, no. 147, CPSY2019-29, pp. 153-157, 2019年7月.
  14. Yuxi Sun, Akram Ben Ahmed, Hideharu Amano, “Accelerating Deep RNN Inference with multiple FPGAs”, 研究報告システム・アーキテクチャ（ARC）,2019-ARC-237(32),1-5 (2019-07-17) , 2188-8574
  15. 池添赳治, 小島拓也, 天野英晴, “不揮発性構成メモリを用いた耐故障性粗粒度再構成可能アーキテクチャ”, 信学技報, vol. 119, no. 208, RECONF2019-28, pp. 39-44, 2019年9月.
  16. ウェイ カイジ, 本田紘規,天野英晴, “二値化したYOLOシステムローコストFPGAでの実装”, 信学技報, vol. 119, no. 208, RECONF2019-32, pp. 63-68, 2019年9月.
  17. 小島拓也, 天野英晴, “CGRAのためのアプリケーションマッピングフレームワークGenMapの実装と実機評価”, 信学技報, vol. 119, no. 282, VLD2019-29, pp. 1-6, 2019年11月.
  18. 茅島秀人, 小島拓也, 奥原　颯, 四手井綱章, 天野英晴, “チップ間誘導結合無線通信技術の実機評価”, 信学技報, vol. 119, no. 286, CPSY2019-48, pp. 59-64, 2019年11月.
  19. 戸村遼平, 小島拓也, 天野英晴, 坂本龍一, 近藤正章, “CNNアクセラレータSNACCの実チップ評価”, 信学技報, vol. 119, no. 286, CPSY2019-49, pp. 65-70, 2019年11月.



2018

受賞

COOL Chips 21 Best Poster Award

  • Kensuke Iizuka, “A multi-FPGA accelerator for GoogLeNet”

CANDAR’18 Outstanding Paper Award

  • Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, and Hideharu Amano, “k-Optimized Path Routing for High-Throughput Data Center Networks,” 2018 Sixth International Symposium on Computing and Networking (CANDAR), Takayama, 2018, pp. 99-105.

SUSCW’18 Best Paper Award

  • Hideki Shimura, Hiroyuki Noda, and Hideharu Amano, “C4: An FPGA-based Compression Algorithm for ExpEther,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 356-362.

IEEE Computer Society Young Author Award 2018

  • 安戸僚汰

電子情報通信学会コンピュータシステム研究会優秀若手発表賞

  • 小島 拓也 “可変パイプラインを持つ低消費電力アクセラレータCCSOTB2によるストリーム処理” (萌芽的コンピュータシステム研究展示会 2018年11月)
  • 野田 裕之 “ホールスラスタ内部解析用PIC法計算のArria 10 SoC FPGAへの実装” (学生・若手研究会 2018年12月)

Journal

  1. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan and Hideharu Amano, “Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E101-D, No.6, pp.1532-1540, Jun 2018. DOI: 10.1587/transinf.2017EDP7308.
  2. Keita Azegami, Hayate Okuhara and Hideharu Amano, “Body Bias Control for Renewable Energy Source with a High Inner Resistance,”, IEEE Transactions on Multi-Scale Computing Systems, 2018. (accepted)
  3. H. Okuhara, A. Ben Ahmed and H. Amano, “Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems,” in IEEE Transactions on Circuits and Systems I: Regular Papers.
    doi: 10.1109/TCSI.2018.2811504
  4. H. Okuhara, A. Ben Ahmed, J. M. Kühn and H. Amano, “Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
    doi: 10.1109/TVLSI.2018.2812893
  5. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, and Hideharu Amano, “Designing High-Performance Interconnection Networks with Host-Switch Graphs”, IEEE Transactions on Parallel and Distributed Systems, vol. 29, no. X, 2018.
    DOI: 10.1109/TPDS.2018.2864286
  6. 増山 滉一朗, 藤田 悠, 奥原 颯, 天野 英晴, “低消費電力再構成可能アクセラレータの実装と評価”, 電子情報通信学会論文誌 D, Vol.J101-D, No.5, pp.729-741, 2018年5月. DOI: 10.14923/transinfj.2017JDP7034

国際会議

  1. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando, Mitaro Namiki, Hideharu Amano, “A Shared Memory Chip for Twin-Tower of Chips”, Proc. of The 21th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI2018),pp.353-358, March 2018.
  2. Ryosuke Kazami, Hayate Okuhara, Hideharu Amano, “Design Automation Methodology of a Critical Path Monitor for Adaptive Voltage Controls,” in Proc. of The COOLCHIPS21, pp.1-3, April 2018.
  3. Kazusa Musha, Tomohiro Kudoh and Hideharu Amano, “Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud”, Proc. of the International Simposium on Applied Reconfigurable Computing (ARC), 2018.
  4. Kazuei Hironaka, Nguyen Anh Vu Doan and Hideharu Amano, “Towards an optimized multi FPGA architecture with STDM network: a preliminary study”, Proc. of the International Simposium on Applied Reconfigurable Computing (ARC), 2018.
  5. Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, and Hideharu Amano, “Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC”, in Proc. of 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Budapest, Hungary, April 2018.
  6. Ryota Yasudo, Ana Lucia Varbanescu, Jose Gabriel Figueiredo Coutinho, Wayne Luk, and Hideharu Amano, “Performance Prediction for Large-scale Heterogeneous Platforms”, in Proc. of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, April/May 2018.
  7. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano, “Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), June, 2018, Toronto, Canada.
  8. Takuya Kojima and Hideharu Amano, “A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures”, in Proc. of 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 239-242, August, 2018, Dublin, Ireland.
  9. Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, ”Adaptive Body Bias Control Scheme for Ultra Low-power Network-on-Chip Systems”, In Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-18), Hanoi, Vietnam, pp. – , September, 2018.
  10. Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, ”AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation”, In Proc. of the 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS-2018), Turin, Italy, pp. 44-51, October, 2018.
  11. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, and Hideharu Amano, “k-Optimized Path Routing for High-Throughput Data Center Networks,” 2018 Sixth International Symposium on Computing and Networking (CANDAR), Takayama, 2018, pp. 99-105.
  12. Tomohiro Totoki, Michihiro Koibuchi, and Hideharu Amano, “An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 363-369.
  13. Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, “An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 182-185.
  14. Hideki Shimura, Hiroyuki Noda, and Hideharu Amano, “C4: An FPGA-based Compression Algorithm for ExpEther,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 356-362.
  15. Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami, “A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops,” 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2018, pp. 1-6.
  16. Kaijie Wei, Koki Honda and Hideharu Amano, “FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks,” 2018 International Conference on Field-Programmable Technology (FPT), 2018, pp. 425-428.
  17. Ryota Yasudo, Jose Gabriel Figueiredo Continho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, and Tobias Becker, “Performance Estimation for Exascale Reconfigurable Dataflow Platforms”, in Proc. of the International Conference on Field-Programmable Technology, Naha, Japan, December 2018.

国内研究会

  1. 山内脩吾、武者千嵯、工藤知宏、天野英晴, “マルチFPGAボードによるRecurrent Neural Networkの高速化”, 信学技報, vol. 117, no. 378, CPSY2017-106, pp. 1-6, 2018年1月
  2. 丹羽直也, 十時知滉, 松谷宏紀, 鯉渕道紘, 天野英晴, “3次元DRAM-プロセッサ積層の温度と性能”, 信学技報, vol. 117, no. 378, CPSY2017-110, pp. 25-29, 2018年1月.
  3. 風見亮佑, 奥原 颯, 天野英晴, “適応的電圧制御用クリティカルパスモニタの設計と実装”, 信学技報, vol. 117, no. 479, CPSY2017-139, pp. 125-130, 2018年3月.
  4. 飯塚健介, 武者千嵯, 天野英晴, “マルチFPGA上でのGoogLeNet実装”, 信学技報, vol. 117, no. 479, CPSY2017-141, pp. 191-196, 2018年3月.
  5. 松下 悠亮, 小島 拓也, 門本 淳一郎, 黒田 忠広, 天野 英晴, “マルチコア積層システム Cube-2 の実装と評価”, 情報処理学会第80回全国大会講演論文集, pp.1:81–1:82, 2018年3月.
  6. 寺嶋 爽花, 小島 拓也, 奥原 颯, 松下 悠亮, 安藤 尚輝, 並木 美太郎, 天野 英晴, “ツインタワーのためのメモリチップ”, 情報処理学会第80回全国大会講演論文集, pp.1:87–1:88, 2018年3月.
  7. 小島 拓也, 安藤 尚樹, 天野 英晴, “可変構造パイプラインを持つ粗粒度再構成アクセラレータCCSOTB2”, 情報処理学会第80回全国大会講演論文集, pp.1:89–1:90, 2018年3月.
  8. 奥原颯, ベンアメド アクラム, 天野 英晴, 「低電力プロセッサを実現するボディバイアス制御機構の実チップ評価」、情報処理学会第80回全国大会講演論文集, 3A-04, 2018年3月.
  9. 河野隆太, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, “ルーティングアルゴリズムによる通信帯域の測定と理解”, 電子情報通信学会技術研究報告, vol. 118, no. 165, CPSY2018-23, pp. 133-138, (SWoPP’18), 2018年7月.
  10. 丹羽直也, 十時知滉, 松谷宏紀, 鯉渕道紘, 天野英晴, “3D Network-on-Chip (3D NoC)における遅延が実行時間に与える影響の評価モデルの提案 ～ アプリケーション特性を反映したプロセッサ性能評価モデル ～”, 信学技報, vol. 118, no. 165, CPSY2018-22, pp. 127-132, 2018年7月.
  11. 池添赳治, 天野英晴, 赤池純也, 宇佐美公良, 工藤優, 平賀啓三, 周藤悠介, 屋上公二郎, “省電力型不揮発FFを用いた粗粒度再構成可能アクセラレータ”, 信学技報, vol. 118, no. 165, CPSY2018-32, pp. 229-234, 2018年7月.
  12. 小島拓也, 安藤尚樹, 松下悠亮, 奥原 颯, Nguyen Anh Vu Doan, 天野英晴, “多目的遺伝的アルゴリズムを用いたCGRAマッピング最適化手法と実チップ評価”, 信学技報, vol. 118, no. 215, RECONF2018-31, pp. 67-72, 2018年9月.
  13. 畔上佳太, 武者千嵯, 弘中和衛・Akram Ben Ahmed, 天野英晴, “マルチFPGAボード間通信を⾏うスイッチの開発”, 信学技報, vol. 118, no. 215, RECONF2018-29, pp. 55-59, 2018年9月.
  14. 小島拓也, 安藤尚樹, 松下悠亮, 奥原 颯, Nguyen Anh Vu Doan, 天野英晴, “可変パイプラインを持つ低消費電力アクセラレータCCSOTB2によるストリーム処理”, 信学技報, vol. 118, no. 325, CPSY2018-33, pp. 1-5, 2018年11月.
  15. 武者 千嵯, AkramBen Ahmed, 工藤 知宏, 天野 英晴, “FPGAスイッチボードへの深層学習アプリケーションの実装”, 信学技報, vol. 118, no. 340, RECONF2018-40, pp. 33-38, 2018年12月.
  16. 小島拓也, 天野英晴, “3次元積層型CGRAのためのアプリケーション割り当て手法の検討”, 信学技報, vol. 118, no. 375, CPSY2018-51, pp. 37-42, 2018年12月.
  17. 野田裕之, 宮島敬明, 藤田直行, 天野英晴, “ホールスラスタ内部解析用PIC法計算のArria 10 SoC FPGAへの実装”, 信学技報, vol. 118, no. 375, CPSY2018-75, pp. 119-124, 2018年12月.
  18. 寺嶋爽花, 小島拓也, 武者千嵯, 奥原 颯, 天野英晴, “ツインタワー型共有メモリチップを用いたCNNアプリケーションの高速化”, 信学技報, vol. 118, no. 375, CPSY2018-76, pp. 125-130, 2018年12月.
  19. 茅島秀人, 小島拓也, 奥原 颯, 天野英晴, “誘導結合ThruChip Interfaceの検証方式の実チップ実装”, 信学技報, vol. 118, no. 339, CPSY2018-42, pp. 53-58, 2018年12月.
  20. 十時知滉, 鯉渕道紘, 天野英晴, “多様な積層手法のための温度モデリングツールHotSpot6.0の拡張”, 信学技報, vol. 118, no. 339, CPSY2018-43, pp. 59-64, 2018年12月.
  21. 河野 隆太, 安戸 僚汰, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, “高スループットな相互結合網のためのスケーラブルな複数経路選択手法”, 信学技報, CPSY2018-38, Vol.118, No.339, pp.11–16, 2018年12月.



2017

受賞

テレコム学生技術賞

  • Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, “Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers”, IEEE Transactions on Computers.

情報処理学会ARC研究会若手優秀研究賞

  • 畔上佳太 “自然エネルギーによる低電力リコンフィギャラブルアクセラレータの動作”

CoolChips 20 Featured Poster Award

  • K.Musha, “CNN Acceleration on Multi-FPGA System”

Design Gaia 2017 IEEE CEDA AJJC Design Gaia Best Poster Award 2017

  • H. Okuhara, “Real chip evaluation of a low-power overhead body bias controller”

Journal

  1. A.Nomura, Y.Matsushita, J.Kadomoto, H.Matsutani, T.Kuroda, H.Amano, “Escalator Network for a
    3D Chip Stack with Inductive Coupling ThruChip Interface,” International Journal of Network and Computing, (Accepted)
  2. T.Okubo, M.Sit, H.Amano, R.Takata, R.Sakamoto, M.Kondo, “A Software Development Environment for a Multi-chip Convolutional Network Accelerator,” International Journal of Computer Application, Vol.24, No.2, June 2017.
  3. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing”, IEICE Transactions on Information and Systems, Vol.E100-D, No.8, pp.1798–1806, Aug 2017. DOI: 10.1587/transinf.2016EDP7477
  4. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano, “Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator”, IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.2828–2836, Dec 2017. DOI: 10.1587/transinf.2017PAP0013
  5. Hayate Okuhara,Yu Fujita, Kimiyoshi Usami, and Hideharu Amano, “Power Optimization Methodology for Ultra Low Power Microcontroller with Silicon on Thin BOX MOSFET”, IEEE Tran. on Very Large Scale Integration Systems, Vol.25, Issue4, pp.1578 – 1582, 2017. DOI: 10.1109/TVLSI.2016.2635675
  6. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “A Layout-Oriented Routing Method for Low-Latency HPC Networks”, IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.2796-2807, Dec 2017. DOI: 10.1587/transinf.2017PAP0019

国際会議

  1. Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kuehn, Hideharu Amano, “Leveraging Asymmetric Body Bias Control for Low Power LSI Design,” COOLCHIPS20, April, 2017.
  2. T.Ohkubo, R.Takata, R.Sakamoto, M.Kondo, H.Amano, “NAMACHA: A software development environment for a mutli-chip convolutional network accelerator,” CATA2017, March, 2017.
  3. Keita Azegami, Hayate Okuhara, Hideharu Amano, “Body Bias Control for Renewable Energy Source with a High Inner Resistance”, COOLCHIPS20, April, 2017.
  4. Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano, “Implementation of the PIC method’s aggregation process on a SoC FPGA to avoid RAW hazards using reduction”, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 20), April, 2017.
  5. Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita and Hideharu Amano, “Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), June, 2017, Bochum, DE.
  6. Takahiro Kaneda, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano, “Performance Evaluation of PEACH3: Field Programmable Gate Array Switch for Tightly Coupled Accelerators,” International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), June, 2017.
  7. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amaon, “Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks,” 46th International Conference on Parallel Processing (ICPP-2017), August, 2017.
  8. Naoki Nishikawa, Hideharu Amano, Keisuke Iwai, “Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU,” 11th International Conference on Network and System Security (NSS-2017), August, 2017.
  9. Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano, “Accelerator-in-Switch: a framework for tightly couple switching hub and an accelerator with FPGA” 27th International Conference on Field Programmable Logic and Applications (FPL2017), Sept., 2017.
  10. C. Cortes, H.Amano, “Break Even Time Analysis Using Empirical Overhead Parameters for Embedded Systems on SOTB Technology,” Design of Circuits and Integrated Systems Conference, Nov. 2017
  11. H.Nakahara, N.A.V.Doan, R.Yasudo, H.Amaon, “XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs,” NOCS2017, Oct. 2017
  12. K.Usami, S.Kogure, Y.Yoshida, R.Magasaki, H.Amano, “Level-shifter Free Approach for Multi-VDD SOTB employing Adaptive Vt Modulation for pMOSFET,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Oct. 2017
  13. N.A.V.Doan, Y.Matsushita, N.Ando, H.Okuhara, H.Amano, “Multi-Objective Optimization for Application Mapping and Body Boas COntrol on a CGRA,” IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Sept. 2017
  14. R.Sakamoto, R.Takata, J.Ishii, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano, “The Design and Implementation of Scalable Deep Neural Network Accelerator Cores,”IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Sept. 2017
  15. T. Kojima, N. Ando, H. Okuhara, N. A. V. Doan and H. Amano, “Body bias optimization for variable pipelined CGRA,” 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, Sept. 2017, pp. 1-4.
  16. H.Nakahara, R.Yasudo, H.Matsutani, H.Amano, H.Koibuchi, “3D layout of Spidergon, Flattened Butterfly and Dragonfly on a chip stack with inductive coupling through chip interface,” The 14th International Symposium on Pervasive Systems, Algorithms, and Networks (I-SPAN2017), June, 2017.
  17. C.Cortes, H.Amano, “Switching Region Analysis for SOTB Technology,” 10th International Caribbean Conference on Devices, Circuits and Systems, June. 2017
  18. T. Kojima, N. Ando, H. Okuhara and H. Amano, “Glitch-aware variable pipeline optimization for CGRAs,” 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2017, pp. 1-6.
  19. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies”, Proc. of the IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS’17), pp.664–673, Dec 2017. [Paper]

国内研究会

  1. 鶴田千晴, 金田隆大, 三木洋平, 天野英晴, “PEACH3を用いたN体シミュレーションのオフロード”, 信学技報, vol. 116, no. 510, CPSY2016-157, pp. 369-374, 2017年3月.
  2. 野田裕之, 酒井諒太郎, 宮島敬明, 藤田直行, 天野英晴, “Particle-In-Cell法における集約処理のOpenCLを用いた最適化”, 信学技報, vol. 117, no. 44, CPSY2017-9, pp. 45-50, 2017年5月.
  3. 小島拓也,安藤尚輝,奥原颯,Ng.Doan Anh Vu,天野英晴, “整数計画問題を用いたパイプライン型CGRAのボディバイアス電圧最適化”, 信学技報, vol. 117, no. 46, RECONF2017-16, pp. 81-86, 2017年5月.
  4. 十時知滉, 松谷宏紀, 天野英晴, 藤原一毅, 平澤将一, 鯉渕道紘, “水没プロセッサチップの温度と性能評価”, 信学技報, vol. 117, no. 153, CPSY2017-22, pp. 37-42, 2017年7月.
  5. 天野英晴, 鶴田千晴, “Accelerator-in-Switchのための動的部分再構成”, 信学技報, vol. 117, no. 153, CPSY2017-36, pp. 203-208, 2017年7月.
  6. 畔上佳太, 天野英晴, “内部抵抗の大きい電源によるマイクロコントローラV850の動作”, 信学技報, vol. 117, no. 153, CPSY2017-21, pp. 31-36, 2017年7月.
  7. 志村英樹, 天野英晴, “ExpEtherへの圧縮・伸張機構の開発と実装”, 信学技報, vol. 117, no. 278, CPSY2017-49, pp. 75-80, 2017年11月.
  8. 酒井諒太郎, 宮島敬明, 野田裕之, 藤田直行, 天野英晴, “FPGAベースのSoCを用いた衛星エンジンシミュレーションの高速化”, 信学技報, vol. 117, no. 278, CPSY2017-48, pp. 69-74, 2017年11月.
  9. 武者千嵯, 天野英晴, “大規模マルチFPGAシステムでの深層学習アクセラレート”, 信学技報, vol. 117, no. 278, CPSY2017-40, pp. 1-6, 2017年11月.
  10. 小島拓也,安藤尚輝,奥原颯,天野英晴, “グリッチ削減のためのパイプライン構造最適化”, 信学技報, vol. 117, no. 279, RECONF2017-41, pp. 25-30, 2017年11月.
  11. 安藤尚輝,小島拓也,天野英晴, “可変パイプラインCGRAの実チップ評価”, 信学技報, vol. 117, no. 279, RECONF2017-41, pp. 19-24, 2017年11月.
  12. 河野 隆太, 安戸 僚汰, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, “ターンモデルベースの不規則網向けルーティング”, 電子情報通信学会技術研究報告, CPSY2017-44, Vol.117, No.278, pp.23–28, Nov 2017.
  13. 寺嶋爽花, 小島拓也, 奥原颯, 松下悠亮, 安藤尚輝, 並木美太郎, 天野英晴, “ツインタワー用共有メモリチップの開発”, 信学技報, vol. 117, no. 273, VLD2017-34, pp. 43-48, 2017年11月.
  14. 奥原 颯, ベンアメド アクラム, 天野 英晴, “超低電力ボディバアイス調節機構の実チップ評価”, 信学技報, vol.117, no.276, ICD2017-40, pp.9-14, 2017年11月.



2016

受賞

IPSJ Best Paper Award

  • Takaaki Miyajima, David Thomas, Hideharu Amano, “Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms”, IPSJ Transactions on System LSI Design Methodology Vol. 8 (2015) pp. 105-115

CANDAR Best Paper Award

  • Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “LOREN: A Scalable Routing Method for Layout-conscious Random Topologies”, the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.

第7回相磯杯 The 2nd RECONF/CPSY/ARC/GI Trax デザインコンペティション

  • 一般部門3位 中原浩
  • 一般部門5位 大久保徹以
  • エンベッデッド部門6位 金田隆大

山下記念研究賞

  • 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, “分散ルータによる高性能NoC”, 信学技報, vol. 115, no. 399, CPSY2015-127, pp. 149-154, 2016年1月.

HiPEAC Paper Award

  • Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel “Leveraging FDSOI through body bias domain partitioning and bias search”, DAC2016, July, 2016.

電子情報通信学会 集積回路研究専門委員会 研究会優秀若手講演賞

  • 河野 隆太, 中原 浩, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘, “HPCネットワーク用ランダムトポロジ向けの低遅延な分散ルーティング手法”, 信学技報, vol. 115, no. 374, CPSY2015-103, pp. 105-110, 2015年12月.

電子情報通信学会リコンフィギュラブルシステム研究会若手優秀研究賞

  • 安藤尚輝、増山滉一朗、藤田悠、天野英晴 “粗粒度再構成可能アクセラレータCMAにおけるパイプライン分割の検討”、信学技報, vol. 115, no. 400, RECONF2015-61, pp. 13-18, 2016年1月.

情報処理学会システム・アーキテクチャ研究会若手奨励賞

  • 畔上 佳太、増山 滉一朗、奥原 颯、天野 英晴 “自然エネルギーによる低電力リコンフィギュアラブルアクセラレータの動作”、信学技報, vol. 116, no. 416, CPSY2016-130, pp. 159-164, 2017年1月.

論文誌

  1. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, “Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers”, IEEE Transactions on Computers.
  2. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface”, IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Vol.E99-D, No.12, pp.xxx-xxx, Dec 2016. (to appear)
  3. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, and Hideharu Amano, ”Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems”, IEICE Transactions on Electronics, Vol. E99-C No. 8, pp. 909-917, August 2016.
  4. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, “Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24,No.2pp.493-506, 2016
  5. 奥原 颯、 北森邦明、 宇佐美公良、天野英晴 “SOTB MOSFETを用いた汎用マイクロコントローラV850の動的ボディバイアス制御の検討”、情報処理学会論文誌、Vol57、No.2、pp708-717、2016。

国際会議

  1. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “LOREN: A Scalable Routing Method for Layout-conscious Random Topologies”, Proc. of the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.
  2. Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano, “On-the-fly data compression/decompression mechanism with ExpEther”, Proc. of the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.
  3. Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano, “Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface”, Proc. of the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.
  4. Carlos Cesar Cortes Torres, Hayate Okuhara, Akram Ben Ahmed, Nobuyuki Yamasaki,
    Hideharu Amano, “Analysis of Body Bias Control for Real Time Systems”, Proc. of the 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Oct. 2016.
  5. Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano, “Acceleration of Full-PIC simulation on a CPU-FPGA tightly coupled environment”, Proc. of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep 2016.
  6. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano and Hideharu Amano “Body Bias Grain Size Exploration for a Coarse Grained Reconfigurable Accelerator”, Proc. of the 26th The International Conference on Field-Programmable Logic and Applications (FPL),2016.
  7. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel “Leveraging FDSOI through body bias domain partitioning and bias search”, DAC2016, July, 2016.
  8. Takahiro Kaneda, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano “Performance Evaluation of PEACH3: an FPGA switch for tightly coupled accelerators”, Proc. of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), 2016.
  9. Takuji Mitsuishi, Takahiro Kaneda, Hideharu Amano and Sunao Torii “Breadth-first Search on Suiren: a compact supercomputer”, Proc. of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), 2016.
  10. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, “ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free”, Proc. of the 15th IEEE/ACIS International Conference on Computer and Information Science(ICIS), 2016.
  11. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel, “Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search”, Proc. of the 53nd Design Automation Conference(DAC), 2016.
  12. Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano, “On-the-fly data compression for ExpEther NIC” , Proc. of the 19th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIX), Poster session, Apr. 2016.
  13. Ryotaro Sakai, Takaaki Miyajima, Naru Sugimoto, Naoyuki Fujita, and Hideharu Amano, “Construction of an environment for satellite engine simulation with Zynq”, IEEE Symposium on Low-Power and High-Speed Chips (IEEE Cool Chips XIX), April 2016.
  14. Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, “Randomizing Packet Memory Networks for Low-latency Processor-memory Communication,” Proc. of the 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 17-19 Feb. 2016.
  15. Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano, “Zynq Cluster for CFD Parametric Survey”, Proc. of the International Simposium on Applied Reconfigurable Computing (ARC), 2016.

国内研究会

  1. 野田裕之, 酒井諒太郎, 宮島敬明, 藤田直行, 天野英晴, “ホールスラスタ・シミュレーションにおける割付処理のAltera SDK for OpenCLを用いた高速化”, 信学技報, vol. 116, no. 510, CPSY2016-158, pp. 375-380, 2017年3月.
  2. 小島拓也, 安藤尚輝, 松下悠亮, 奥原颯, 天野英晴, “パイプライン段数とボディバイアス電圧制御によるパイプライン型CGRAの電力削減手法の検討”, 信学技報, vol. 116, no. 510, CPSY2016-140, pp. 51-56, 2017年3月.
  3. 大久保徹以, 小島拓也, 天野英晴, 高田遼, 石井潤, 坂本龍一, 近藤正章, 中村宏, “無線3次元積層チップを用いたDeep Learningアクセラレータのコンパイラツールチェーン”, 信学技報, vol. 116, no. 510, CPSY2016-155, pp. 357-362, 2017年3月.
  4. 畔上佳太,増山滉一朗,奥原 颯,天野英晴, “自然エネルギーによる低電力リコンフィギュアラブルアクセラレータの動作”, 信学技報, vol. 116, no. 416, CPSY2016-130, pp. 159-164, 2017年1月.
  5. 奥原 颯, Akram Ben Ahmed, 天野英晴, “オンチップボディバイアス調節機構アーキテクチャの提案と実装”, 信学技報, vol. 116, no. 336, CPSY2016-54, pp. 35-40, 2016年11月.
  6. 河野 隆太, 中原 浩, 藤原 一毅, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, “配線長制限ランダムトポロジ向けのスケーラブルなルーティング手法”, 第15回情報科学技術フォーラム, vol.1, pp.337–338, 2016年9月.
  7. 奥原 颯, 天野 英晴, “FD-SOIテクノロジを用いた最適なボディバイアスバランスの検討”, 第15回情報科学技術フォーラム, vol.1, pp.319–320, 2016年9月.
  8. 酒井 諒太郎, 宮島 敬明, 杉本 成, 藤田 直行, 天野 英晴, “Zynqを用いたFull-PIC法の高速化の検討”, 第15回情報科学技術フォーラム, 2016年9月.
  9. 安戸僚汰, 藤原一毅, 鯉渕道紘, 松谷宏紀, 天野英晴, 中村維男, “非正則グラフによる低遅延相互結合網の検討”, 電子情報通信学会技術研究報告, vol. 116, no. 177, CPSY2016-39, pp. 281-286 / 情報処理学会研究報告, vol. 2016-ARC-221, no. 44, pp. 1-6 (SWoPP’16), 2016年8月.
  10. 酒井 諒太郎, 宮島 敬明, 杉本 成, 藤田 直行, 天野 英晴, “Zynqを用いた衛星エンジンシミュレーションの高速化の検討”, 信学技報, vol. 116, no. 177, CPSY2016-36, pp. 263-268, 2016年8月.
  11. 河野 隆太, 中原 浩, 藤原 一毅, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, “HPC向けネットワークのための幾何ルーティング”, LSIとシステムのワークショップ2016, ポスターセッション, no.15, 2016年5月.
  12. 奥原 颯, Johannes Maximilian Kuehn, Akram Ben Ahmed, 天野英晴, “細粒度ボディバイアス制御を用いたCGRAのリーク電流最小化”, 信学技報, vol. 116, no. 53, RECONF2016-15, pp. 71-76, 2016年5月.
  13. 河野 隆太, 中原 浩, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘, “決定的デッドロックフリールーティングのための効率的な仮想チャネル割り当て手法”, 電子情報通信学会技術研究報告 CPSY2015-148, vol.115, no.518, pp.163–168, 2016年3月.
  14. 河野 隆太, 中原 浩, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘, “オフチップ相互結合網向け不規則トポロジのための容易に実装可能なルーティングアルゴリズム”, 情報処理学会第78 回全国大会講演論文集, pp.1:15–1:16, 2016年3月.
  15. 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, “分散ルータによる高性能NoC”, 信学技報, vol. 115, no. 399, CPSY2015-127, pp. 149-154, 2016年1月.



2015

受賞

Best Paper Award

  • Yu Fujita, Hayate Okuhara, Koichiro Masuyama, and Hideharu Amano, “Power optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB”, Proc. of The Third International Symposium on Computing and Networking (CANDAR), Dec 2015
  • Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Masayuki Umemura and Hideharu Amano, “Off-loading LET generation to PEACH2: A switching hub for high performance GPU clusters”, Proc. of the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART), May 2015.

Best Poster Award

  • Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “Ultra Low Power Reconfigurable Accelerator CMA-SOTB-2”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.

ディペンダブルコンピューティング研究会優秀若手講演賞

  • 野村明生・藤田悠・松谷宏紀・天野英晴（慶大）, 誘電結合チップ間通信を用いた共有バスアーキテクチャ，2015年4月

Journal

  1. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham “A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode,” Vol.E98-C No.7, pp.536-543. 2015.
  2. Takaaki Miyajima, David Thomas, Hideharu Amano, “A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms”, Journal of Information Processing, vol.23, no.2, pp.153-162, 2015.

国際会議

  1. Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano, “Trax Solver on Zynq with Deep Q-Network”, Proc. of the International Conference on Field-Programmable Technology (ICFPT), December 2015.
  2. Koichiro Masuyama, Yu Fujita, Hayate Okuhara and Hideharu Amano, “A 297MOPS/0.4mW Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA-SOTB-2”, Proc. of The 10th International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2015.
  3. Yu Fujita, Hayate Okuhara, Koichiro Masuyama, and Hideharu Amano, “Power optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB”, Proc. of The Third International Symposium on Computing and Networking (CANDAR), pp.xxx-xxx, 2015.(to appear)
  4. Akio Nomura,Yu Fujita, Hiroki Matsutani,and Hideharu Amano, “3D Shared Bus Architecture Using Inductive Coupling Interconnect”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.xxx-xxx, Sep 2015.
  5. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.41-48, Sep 2015.
  6. Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano, “REDUCTION CALCULATIOR IN AN FPGA BASED SWITCHING HUB FOR HIGH PERFORMANCE CLUSTERS”, Proc. of the 25th International Conference on Field-programmable Logic and Applications (FPL), September 2015.
  7. Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “7 MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2”, Proc. of the 25th International Conference on Field-programmable Logic and Applications (FPL), September 2015.
  8. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano and Tadao Nakamura, “On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck”, Proc. of the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), September 2015.
  9. Seiichi Tade, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, “A Metamorphotic Network-on-Chip for Various Types of Parallel Applications”, Proc. of the IEEE International Conferene on Application-specific Systems, Architectures and Processors (ASAP), July 2015.
  10. Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, and Hideharu Amano, “An Optimal Power Supply And Body Bias Voltage for a Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET”, Proc. of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015.
  11. Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan and Hideharu Amano, “Breadth First Search on Cost-efficient Multi-GPU Systems”, Proc. of the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART), May 2015.
  12. Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Masayuki Umemura and Hideharu Amano, “Off-loading LET generation to PEACH2: A switching hub for high performance GPU clusters”, Proc. of the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART), May 2015. (Best paper award)
  13. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmannz, Wolfgang Rosenstiel, “Fined-Grained Body Biasing for Frequency Scaling in Advanced SOI Processes”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Apr. 2015.
  14. Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano, “A Leakage Current Monitor Circuit Using Silicon on Thin BOX MOSFET for Dynamic Back Gate Bias Control”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Apr. 2015.
  15. Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “Ultra Low Power Reconfigurable Accelerator CMA-SOTB-2”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015. (Best poster award)
  16. Takahiro Kaneda, Takuji Mitsuishi, Yuki Katsuta, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku, “Parallel Processing of Graph Search by Tightly Coupled Accelerator”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  17. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Staggered Stacking: Connecting Many Small Chips Using ThruChip Interface”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  18. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, “3D Bus Architecture using Inductive Coupling ThruChip-Interface”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  19. Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Takuji Mitsuishi, Naru Sugimoto, Hideharu Amano, “Off-loading LET generator in PEACH2 : A Switching Hub for High Performance GPU Clusters”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  20. Mao Hatto, Takaaki Miyajima, Hideharu Amano, “Data Reduction and Parallelization for Human Detection System”, Proc. of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.134-139, Mar. 2015.
  21. Hayate Okuhara, Hideharu Amano, “Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET”, Proc. of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.299-304, Mar. 2015.
  22. Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel, “Spatial and temporal granularity limits of body biasing in UTBB-FDSOI”, Proc. of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2015.
  23. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, “Optimized Core-links for Low-latency NoCs”, Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pp.172-176, Mar. 2015.

国内研究会

  1. 奥原 颯, 藤田 悠, 北森邦明, 宇佐美公良, 天野英晴, “電力のモデル式に基づく汎用CPUの電力最適化”, 信学技報, vol. 115, no. 374, CPSY2015-101, pp. 93-98, 2015年12月.
  2. 増山滉一朗, 藤田 悠, 奥原 颯, 天野英晴, “超低電力再構成可能アクセラレータCCSOTBの実装と評価”, 信学技報, vol. 115, no. 374, CPSY2015-102, pp. 99-103, 2015年12月.
  3. 河野隆太, 中原 浩, 藤原一毅, 松谷宏紀, 天野英晴, 鯉渕道紘, “HPCネットワーク用ランダムトポロジ向けの低遅延な分散ルーティング手法”, 信学技報, vol. 115, no. 374, CPSY2015-103, pp. 105-110, 2015年12月.
  4. 中原 浩, 藤木大地, 蓼 誠一, 安戸僚汰, 河野隆太, 松谷宏紀, 鯉渕道紘, 中野浩嗣, 天野英晴, “三次元積層チップにおける最大配線長制限下トポロジ最適化”, 信学技報, vol. 115, no. 374, CPSY2015-104, pp. 111-116, 2015年12月.
  5. 鶴田千晴, 金田隆大, 三木洋平, 天野英晴, “PEACH2を用いた重力計算アプリケーションにおけるFPGA/GPU協調動作”, 信学技報, vol. 115, no. 374, CPSY2015-105, pp. 117-122, 2015年12月.
  6. 天野英晴, 櫻井祐市, 鶴田千晴, “スイッチ内アクセラレーションの実現のための部分再構成”, 信学技報, vol. 115, no. 343, RECONF2015-49, pp. 9-12, 2015年12月.
  7. 野村明生, 松谷宏紀, 竹 康宏, 並木美太郎, 黒田忠広, 天野英晴, “ThruChip Interfaceを用いた直線状ネットワークの予備評価”, 信学技報, vol. 115, no. 342, CPSY2015-68, pp. 39-44, 2015年12月.
  8. 奥原 颯, 小出知明, Johannes Maximilian Kuehn, Akram Ben Ahmed, 石橋孝一郎, 天野英晴, “SOTB MOSFETを用いた低電力マイクロコントローラの動的基板バイアス制御機構の実装と予備評価”, 信学技報, vol. 115, no. 342, CPSY2015-71, pp. 57-62, 2015年12月.
  9. 増山滉一朗, 藤田 悠, 奥原 颯, 天野英晴, “レモン電池で動作する低電力アクセラレータCMA-SOTB-2”, 信学技報, vol. 115, no. 243, CPSY2015-60, pp. 71-76, 2015年10月.
  10. 杉本 成, 天野英晴, “CFDパラメトリックサーベイ用ZYNQクラスタ”, 信学技報, vol. 115, no. 228, RECONF2015-39, pp. 39-44, 2015年9月.
  11. 藤木大地, 松谷宏紀, 鯉渕道紘, 天野英晴, “Hybrid Memory Cubeを用いたランダムメモリネットワーク”, 信学技報, vol. 115, no. 174, CPSY2015-21, pp. 65-70, 2015年8月.
  12. 蓼 誠一, 鯉渕道紘, 松谷宏紀, 天野英晴, “再構成可能ネットワークオンチップを用いた耐故障性向上”, 信学技報, vol. 115, no. 174, CPSY2015-28, pp. 143-148, 2015年8月.
  13. 中原 浩, 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, “三次元積層チップへの高性能既存トポロジレイアウト法”, 信学技報, vol. 115, no. 174, CPSY2015-43, pp. 275-280, 2015年8月.
  14. 天野英晴, 片桐 徹, “STmicro28nmプロセスを用いた動的再構成可能プロセッサMuCCRA-4の実チップ評価”, 信学技報, vol. 115, no. 109, RECONF2015-21, pp. 113-118, 2015年6月.
  15. 増山滉一朗, 藤田 悠, 奥原 颯, 天野英晴, “低電力アクセラレータCMA-SOTB-2の実装と評価”, 信学技報, vol. 115, no. 109, RECONF2015-2, pp. 7-12, 2015年6月.
  16. 鶴田千晴, 久原拓也, 三木洋平, 天野英晴, “重力計算アプリケーションのPEACH2へのオフローディング”, 信学技報, vol. 115, no. 7, CPSY2015-2, pp. 7-12, 2015年4月.
  17. 野村明生, 藤田 悠, 松谷宏紀, 天野英晴, “誘導結合チップ間通信を用いた共有バスアーキテクチャ”, 信学技報, vol. 115, no. 7, CPSY2015-4, pp. 19-24, 2015年4月.
  18. 藤田 悠, 奥原 颯, 増山滉一朗, 天野英晴, “低電力リコンフィギャラブルアクセラレータCMA-SOTBの電力最適化”, 信学技報, vol. 114, no. 506, CPSY2014-174, pp. 71-76, 2015年3月.



2014

受賞

Best Paper Award

  • Yu Fujita, Kimiyoshi Usami, Hideharu Amano, “A Thermal Management System for Building Block Computing System,” Proc. of Enbedded Multicore/Many-core System on Chips, September 2014.

Featured Poster Award

  • Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano, “Voltage control considering the chip temperature in the three-dimensional stacked multi-core processors,” Proc. of the COOL Chips XVII (Poster), April 2014.
  • Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,
    “A Configurable Switch Mechanism for Random NoCs,” Proc. of the COOL Chips XVII (Poster), April 2014.

電子情報通信学会コンピュータシステム研究会若手研究賞

  • 加賀美崇紘 “ワイヤレス垂直バスを用いた3 次元NoC 向けルーティング手法の拡張” (2013年8月研究会)

Journal

  1. Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano, “A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA”, International Journal of Networking and Computing, Vol.4, No.2, 2014.
  2. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda and Hideharu Amano, “3D NoC with Inductive-Coupling Links for Building-Block SiPs”, IEEE Transaction on Computers, Vol.63, No.3, pp.748–763, March 2014. (DOI:10.1109/TC.2012.249)
  3. Takayuki AKAMINE, Mohamad Sofian ABU TALIP, Yasunori OSANA, Naoyuki FUJITA, Hideharu AMANO,
    Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh, IEICE TRANSACTIONS on Information and Systems Vol.E97-D No.5 pp.1225-1234
  4. Zhang Hao, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,
    Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs, IPSJ Transaction
    on System LSI Design Methodology, Vol..7 pp,27-36.

論文誌(和文)

  1. 河野 隆太, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘, “複数コアリンクを用いた低遅延オンチップトポロジに関する研究”, 電子情報通信学会論文誌 情報・システム, Vol.J97-D, No.3, pp.601-613, Mar 2014.

国際会議

  1. Yu Fujita, Koichiro Masuyama, Hideharu Amano, “Image processing by A 0.3 V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery”, roc. of the International Conference on Field-Programmable Technology (ICFPT), December 2014.
  2. Naru Sugimoto, Hideharu Amano, “Hardware/software co-design architecture for Blokus Duo solver”, Proc. of the International Conference on Field-Programmable Technology (ICFPT), December 2014.
  3. Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, “A Preliminarily Evaluation of PEACH3: A Switching Hub for Tightly Coupled Accelerators”, Proc. of the International Symposium on Computing and Networking (CANDAR), December 2014.
  4. Dipikarani Mishra, Mao Hatto, Takuya Kuhara, Yasunori Osana, Naoyuki Fujita, Hideharu Amano, “FPGA Implementation of Viscous Function in a Package for Computational Fluid Dynamics”, Proc. of the International Symposium on Computing and Networking (CANDAR), December 2014.
  5. Yu Fujita, Kimiyoshi Usami, Hideharu Amano, “A Thermal Management System for Building Block Computing System,” Proc. of Enbedded Multicore/Many-core System on Chips, September 2014.
  6. Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura, “Design of a Low Power NoC Router using Marching Memory Through type,” Proc. of the 8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), September 2014.(DOI:10.1109/NOCS.2014.7008769)
  7. Toru Katagiri, Hideharu Amano, “A high speed design and implementation of dynamically reconfigurable processor using 28nm SOI technology”, Proc. of Field Programable Logic and Applications (FPL), September 2014.
  8. Honlian Su, Yu Fujita, Hideharu Amano, “Body Bias Control for a Coarse Grained Reconfigurable Accelerator Implemented with Silicon on Thin BOX Technology,” Proc. of Field Programable Logic and Applications (FPL), September 2014.
  9. Hideharu Amano, “Block Computing Systems with Wireless Inductive Through Chip Interface”, Proc. of the 6th Workshop on Design for 3D Silicon Integration (Invited), June 2014.
  10. Johannes Maximilian Kühn, Hideharu Amano, Toru Katagiri, Wolfgang Rosenstiel, “Leakage Reduction using Coarse-Grained Static Body Biasing in a Dynamically Reconfigurable Processor”, Proc. of Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June 2014.
  11. Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano, “Accelerating Breadth First Search on GPU-BOX,” Proc. of Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June 2014.
  12. Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura , ”A low power NoC router using the marching memory through type,” Proc. of the COOL Chips XVII , Apr 2014. (DOI:10.1109/CoolChips.2014.6842960)
  13. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,
    “A Configurable Switch Mechanism for Random NoCs,” Proc. of the COOL Chips XVII (Poster), April 2014.
  14. Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano, “Voltage control considering the chip temperature in the three-dimensional
    stacked multi-core processors,” Proc. of the COOL Chips XVII (Poster), April 2014.
  15. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku, “Task Level Pipelining on Multiple Accelerators via FPGA Switch,” Proc. of Parallel and Distributed Computing and Networks, February 2014.

国内研究会

  1. 奥原 颯, 天野英晴, “リコンフィギャラブルアーキテクチャのためのバックゲートバイアス印加時間解析”, 信学技報, vol. 114, no. 331, RECONF2014-36, pp. 13-18, 2014年11月.
  2. 中原 浩, 松谷宏紀, 鯉渕道紘, 天野英晴, “Castle of Chipsのためのスケーラブルな高性能積層法”, 信学技報, vol. 114, no. 330, CPSY2014-79, pp. 39-44, 2014年11月.
  3. 安戸僚汰, 松谷宏紀, 鯉渕道紘, 天野英晴, 中村維男, “トランスペアレントラッチを用いたNoC向け分散ルータアーキテクチャ”, 信学技報, vol. 114, no. 330, CPSY2014-80, pp. 45-50, 2014年11月.
  4. 金田隆大, 三石拓司, 勝田裕貴, 久原拓也, 塙 敏博, 天野英晴, 朴 泰祐, “Tightly Coupled Acceleratorsによるグラフ探索の並列処理の評価”, 信学技報, vol. 114, no. 302, CPSY2014-65, pp. 63-68, 2014年11月.
  5. 三石拓司, 鈴木 順, 林 佑樹, 管 真樹, 天野英晴, “GPU-BOXにおける中規模グラフに適した並列幅優先探索手法”, 信学技報, vol. 114, no. 302, CPSY2014-66, pp. 69-74, 2014年11月.
  6. 北森邦明, 天野英晴, “SOTBを用いたマイコンの電力最適化”, 信学技報, vol. 114, no. 242, CPSY2014-50, pp. 19-24, 2014年10月.
  7. 宮島敬明, デビッド・トーマス, 天野英晴, “CPU-FPGA環境におけるソフトウェア-ハードウェア混在パイプラインの構築”, 信学技報, vol. 114, no. 223, RECONF2014-27, pp. 57-62, 2014年9月.
  8. 久原拓也, 宮島敬明, 塙 敏博, 天野英晴, “PEACH2への演算機構の実装とその性能評価”, 信学技報, vol. 114, no. 223, RECONF2014-28, pp. 63-68, 2014年9月.
  9. 河野隆太, 藤原一毅, 松谷宏紀, 天野英晴, 鯉渕道紘, “光サーキットの補助による低遅延性及びトポロジ内包性・分割性をもつネットワーク”, 信学技報, vol. 114, no. 155, CPSY2014-20, pp. 61-66, 2014年7月.
  10. 蓼 誠一, 河野隆太, 松谷宏紀, 鯉渕道紘, 天野英晴, “規則・不規則切り替え可能な再構成NoC”, 信学技報, vol. 114, no. 155, CPSY2014-22, pp. 73-78, 2014年7月.
  11. 天野英晴, 久原拓也, 塙 敏博, 児玉祐悦, 朴 泰祐, “PEACH3の基本転送性能の予備評価”, 信学技報, vol. 114, no. 155, CPSY2014-26, pp. 97-102, 2014年7月.
  12. 八藤磨生, 宮島敬明, 松谷宏紀, 天野英晴, “データベース前処理用HOG変換のFPGA実装”, 信学技報, vol. 114, no. 75, RECONF2014-3, pp. 11-16, 2014年6月.
  13. 藤田 悠, 蘇 洪亮, 天野英晴, “低電力リコンフィギャラブルアクセラレータCMA-SOTBのボディバイアス制御”, 信学技報, vol. 114, no. 75, RECONF2014-8, pp. 37-42, 2014年6月.
  14. 勝田裕貴, 宮島敬明, 野村鎮平, 久原拓也, 塙 敏博, 天野英晴, 朴 泰祐, “Tightly Coupled Acceleratorを用いた幅優先探索の高速化”, 信学技報, vol. 114, no. 21, CPSY2014-4, pp. 15-20, 2014年4月.
  15. 河野隆太, 藤原一毅, 松谷宏紀, 天野英晴, 鯉渕道紘, “光サーキットの補助的利用による高いトポロジ内包性を持つHPCインターコネクト”, 信学技報, vol. 113, no. 497, CPSY2013-111, pp. 253-258, 2014年3月.
  16. 藤田 悠, 小泉佑介, 宇野理恵, 天野英晴, “三次元積層マルチコアプロセッサにおけるチップ温度を考慮した電圧制御”, 信学技報, vol. 113, no. 497, CPSY2013-109, pp. 241-246, 2014年3月.
  17. 三石拓司, 野村鎮平, 宮島敬明, 鈴木 順, 林 佑樹, 菅 真樹, 天野英晴, “GPU-BOXにおける幅優先探索の高速化”, 信学技報, vol. 113, no. 497, CPSY2013-108, pp. 235-240, 2014年3月.
  18. 蓼 誠一, 加賀美崇紘, 河野隆太, 松谷宏紀, 鯉渕道紘, 天野英晴, “ランダムNoCのためのコンフィギャラブルスイッチ機構”, 信学技報, vol. 113, no. 418, RECONF2013-77, pp. 125-130, 2014年1月.
  19. 片桐 徹, 天野英晴, “動的再構成プロセッサMuCCRA-4 の実装”, 信学技報, vol. 113, no. 418, RECONF2013-76, pp. 119-124, 2014年1月.
  20. 久原拓也, 宮島敬明, 塙 敏博, 天野英晴, 朴 泰祐, “PEACH2を用いたノード間通信中のFPGA/GPU協調動作”, 信学技報, vol. 113, no. 417, CPSY2013-79, pp. 37-42, 2014年1月.
  21. 杉本 成, 宮島敬明, 久原拓也, 三石拓司, 天野英晴, “Cyber Work BenchによるBlokus Duo AIの実現”, 信学技報, vol. 113, no. 418, RECONF2013-58, pp. 13-18, 2014年1月.



2013

受賞

Best Paper Award

  • Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, “A Case for Wireless 3D NoCs for CMPs”, The 18th Asia and South Pacific Design Automation Conference(ASPDAC’13), Jan 2013.

Best Poster Award

  • Y.Koizumi, N.Miura, Y.Take, H.Matsutani, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura, “Performance and Energy Optimization of a Heterogeneous Multi-Core Processor with Inductive Coupling Links,” CoolChips XVI,April, 2013.

電子情報通信学会コンピュータシステム研究会若手研究賞

  • 伊澤麻衣 低消費電力アクセラレータCMAのコプロセッサ化について 2012年8月研究会
  • 宮島敬明 OpenCVとGPUを対象としたランタイムバイナリアクセラレーション機構の試作と評価 2012年10月研究会
  • 河野隆太 複数ホストリンクを用いたNoC向け低遅延トポロジ 2013年4月研究会

論文誌

  1. M. Sofian Abu Talip, T. Akamine, M.Hatto, Y.Osana, H.Amano, “Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration”, International Journal of Networking and Computing, Vol.3, No.2, pp.289–306, Aug 2013.
  2. A.Akagic, H.Amano, “Design and Implementation of IP-based iSCSI Offload Engine on an FPGA”, IPSJ Trans. System LSI Design Methodology, No.6,pp.112–121,Aug 2013.
  3. A.Akagic, H.Amano, “High-Speed Fully-Adaptable CRC Accelerators”, IEICE Trans. Inf. and Syst.,E96-D,No.6,pp.1299-1308, Jun,2013.
  4. H.Nakamura, W.Wang, Y.Ohta, K.Usami, H.Amano, M.Kondo, M.Namiki, “Fine-Grained Run-Time Power Gating though Co-Optimization of Circuit, Architecture and System Sofware Design”, IEICE Trans. Electron., E-96C, No.4, pp.404-412, Apr 2013.

国際学会

  1. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, and Hideharu Amano, “Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing,” Proc. of Field-Programmable Technology, Dec 2013.
  2. Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, and Hideharu Amano, “A co-processor design of an energy efficient reconfigurable accelerator CMA,” CANDAR 2013, Dec  2013.
  3. K.Kitamori, H.Su, H.Amano, “Power optimization of a micro-controller with Silicon On Thin Buried Oxide,” SASIMI 2013, Oct 2013.
  4. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, ”Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive Coupling Links”, Proc. of the COOL Chips XVI , Apr 2013.
  5. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, ”Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture”, Proc. of the 7th ACM/IEEE International Symposium on Networks-on-Chip(NOCS’13), Apr 2013.
  6. Nobuyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, and Hiroshi Nakamura, ”A Scalable 3D Heterogeneous Multi-Core Processor with Inductive Coupling ThruChip Interface”, Proc. of the COOL Chips XVI , Apr 2013.
  7. Rie Uno, Nobuaki Ozaki, Hideharu Amano, ”Research of PE Array Connection Network for Cool Mega-Array”, Proc. of Int. Workshop on Renewable Computing Systems(WReCS’13), Mar 2013.
  8. Daiki Kugami, Takaaki Miyajima, and Hideharu Amano, ”A circuit division method for High Level synthesis on Multi-FPGA systems”, Proc. of Int. Workshop on Renewable Computing Systems(WReCS’13), Mar 2013.
  9. Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, and Hideharu Amano,  ”An FPGA Acceleration for the Kd-tree Search in Photon Mapping”, Proc. of Int. Synposium on Advanced Reconfigurable Systems, Mar 2013.
  10. Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Michihiro Koibuchi, Tadahiro Kuroda, and Hideharu Amano, ”A Case for Wireless 3D NoCs for CMPs”, Proc. of The 18th Asia and South Pacific Design Automation Conference(ASPDAC’13), Jan 2013.

国内研究会

  1. 加賀美崇紘, 松谷宏紀, 鯉渕道紘, 天野英晴, “チップ間ワイヤレス通信にCSMA/CDバスを用いた3-D NoCアーキテクチャ”, 信学技報, vol. 113, no. 324, CPSY2013-72, pp. 77-82, Nov 2013.
  2. 安戸僚汰, 加賀美崇紘, 天野英晴, 中瀬泰伸，渡邊政志, 大石 司, 清水 徹, 中村維男, “マーチングメモリスルータイプを用いたNoCルータ”, 信学技報, vol. 113, no. 324, CPSY2013-71, pp. 71-76, Nov 2013.
  3. 國上太旗, 宮島敬明, 天野英晴, “高位合成を用いたストリーム処理におけるマルチFPGAシステム向け回路分割手法の提案”, 信学技報, vol. 113, no. 324, CPSY2013-68, pp. 53-58, Nov 2013.
  4. 蘇 洪亮, 天野英晴, “SOTBを用いた低電力リコンフィギャラブルアクセラレータの実チップ評価”, 信学技報, vol. 113, no. 325, RECONF2013-52, pp. 71-76, Nov 2013.
  5. 宇佐美公良, 工藤 優, 松永健作, 小坂 翼, 鶴井敬大, 王 蔚涵, 天野英晴, 坂本龍一, 並木美太郎, 近藤正章, 中村 宏, “細粒度パワーゲーティングを実装したCPU”Geyser-3”の開発と温度に適応した電源遮断制御”, 信学技報, vol. 113, no. 320, VLD2013-80, pp. 135-140, Nov 2013.
  6. 加賀美崇紘,  松谷 宏紀, 鯉渕 道紘, 天野 英晴,  ”ワイヤレス垂直バスを用いた3次元NoC向けルーティング手法の拡張”,  電子情報通信学会技術研究報告 CPSY 2013年8月 (SWoPP’13), Vol.113, No.169, pp.49-54, Aug 2013.
  7. 野村 鎮平, 中浜 徹也, 樋口 淳一,  林 佑樹,  吉川 隆士,  天野 英晴, “ExpEtherを用いたマルチGPUシステムにおけるホスト-デバイス間通信の評価”, 電子情報通信学会技術研究報告 CPSY 2013年8月 (SWoPP’13), Vol.113, No.169, pp.91-96, Aug 2013.
  8. 宇野 理恵, 小崎 信明, 伊澤 麻衣, 津坂 章人, 宮島 敬明, 天野 英晴, “低消費電力アクセラレータCMAの演算終了時間における投機的データ収集機構の実装”, 電子情報通信学会技術研究報告, RECONF2013-11,vol. 113, no. 52, pp. 55-60, May 2013.
  9. 片桐 徹, 天野 英晴, “動的再構成プロセッサの高速化”, 電子情報通信学会技術研究報告, RECONF2013-5,vol. 113, no. 52, pp. 25-30, May 2013.
  10. 宮島 敬明, 久原 拓也, 塙 敏博, デビッド トーマス, 天野英晴,  “TCAノードにおけるランタイムバイナリアクセラレーションの検討”, 電子情報通信学会技術研究報告, RECONF2013-18, vol. 113, no. 52, pp. 97-102, May 2013.
  11. 小崎 信明, 天野 英晴, “低電力アクセラレータCMAのアプリケーションプログラム生成ツールSimple Logicコンパイラの提案”, 電子情報通信学会技術研究報告 CPSY2013-4, Vol.113, No.21, pp.19-24, Apr 2013.
  12. 河野 隆太, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘, “複数ホストリンクを用いたNoC向け低遅延トポロジ”, 電子情報通信学会技術研究報告 CPSY2013-9, Vol.113, No.21, pp.49-54, Apr 2013.
  13. 北森 邦明, 王 蔚涵,  蘇 洪亮, 天野 英晴, “SOTBを用いたマイコンの電力最適化”, 電子情報通信学会技術研究報告 CPSY2012-85, Vol.112, No.481, pp.199-204, Mar 2013.
  14. 津坂 章人, 伊澤 麻衣,  宇野 理恵, 小崎 信明, 天野 英晴, “低消費電力アクセラレータCMAの計算完了の保証機構について”, 電子情報通信学会技術研究報告 CPSY2012-86, Vol.112, No.481, pp.205-210, Mar 2013.
  15. 河野 隆太, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘, “ホストから複数リンクを用いた低遅延ネットワークトポロジ”, 電子情報通信学会技術研究報告 CPSY2012-77, Vol.112, No.376, pp.123-128, Jan 2013.
  16. 野村 鎮平, 中浜 徹也, 樋口 淳一,  林 佑樹,  吉川 隆士,  天野 英晴, “ExpEtherを用いた単一ホスト構成マルチGPUシステムと複数ホスト構成との比較”, 電子情報通信学会技術研究報告 CPSY2012-76, Vol.112, No.376, pp.117-122, Jan 2013.



2012

論文誌

  1. 小崎信明, 宇野理恵, 天野英晴, “超低消費電力粗粒度再構成アクセラレータCMAのPEアレイアーキテクチャの最適化”, 情報処理学会論文誌：コンピューティングシステム, Vol.5, No.5, pp10–22, Oct 2012.
  2. 石井義史, 王蔚涵, 天野英晴, “VLIW型プロセッサにおけるMixed Power Gatingの研究”,  情報処理学会論文誌：コンピューティングシステム, Vol.5, No.5, pp23–32, Oct 2012.
  3. Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano, “Partial reconfiguration of flux limiter functions in MUSCL scheme using FPGA”, IEICE Transactions on Information & Systems, E-95D, No.10, pp2369–2376, Oct 2012.

国際学会

  1. Amila Akagic, and Hideharu Amano, “”A Study of Adaptive co-processors for Cyclic Redundancy Checks on an FPGA”,” Proc. of the International Conference on Field-Programmable Technology, Dec 2012.
  2. Yusuke Koizumi, Eiichi Sasaki, Daisuke Sasaki, Yasuhiro Take, Mitaro Namiki, Tadahiro Kuroda, and Hideharu Amano, “”CMA-CUBE: A SCALABLE RECONFIGURABLE ACCELERATOR WITH 3-D WIRELESS INDUCTIVE COUPLING INTERCONNECT”,” Proc. of the International Conference on Field Programmable Logic and Application, Oct 2012.
  3. Toru Katagiri, Kazuei Hironaka, and Hideharu Amano, “”Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array”,” Proc. of the WReCS 2012 , Sep 2012.
  4.  Shimpei Nomura, Tetusya Nakahama, Junichi Higuchi, Jun Suzuki, Takashi Yoshikawa , and Hideharu Amano, “”The multi-GPU System with ExpEther”,” Proc. of the PDPTA, July 2012.
  5. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D.Frank Hsu, and Henri Casanova, “”A Case for Random Shortcut Topologies for HPC Interconnects”,” Proc. of the ISCA, June 2012.
  6. Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, and Hideharu Amano, “”Trade-off analysis of Fine-grained Power Gating Methods for Functional Units in a CPU ”,” Proc. of the COOL Chips XV , April 2012.
  7. Toru Katagiri, Kazuei Hironaka, and Hideharu Amano, “”Extension of memory controller equipped with MuCCRA-3”,” Proc. of the COOL Chips XV (Poster), April 2012.
  8. Yusuke Koizumi, Eiichi Sasaki, Mitaro Namiki, and Hideharu Amano, “”Application Development for a Heterogeneous Multi-Core Processor”,” Proc. of the COOL Chips XV (Poster), April 2012.
  9. Rie Uno, Nobuaki Ozaki, and Hideharu Amano, “”Design Exploration of PE Array Networks for Cool Mega Array”,” Proc. of the COOL Chips XV (Poster), April 2012.
  10. Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, and Hideharu Amano, “” Cost effective implementation of flux limiter functions using partial reconfiguration ”,” Proc. of the ARC 2012, Mar 2012.
  11. Eiichi Sasaki, Daisuke Sasaki, Ikan Wang, Yusuke Koizumi, and Hideharu Amano, “” Message Passing Direct Memory Access Transfer Method for Inter-Chip Network ”,” Proc. of SASIMI 2012, March 2012.
  12. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, and Hideharu Amano, “” Vertical link on/off control methods for wireless 3-D NoCs ”,” Proc. of the ARCS 2012, Feb 2012.
  13. Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, and Hideharu Amano, “” CMA-2 : The second prototype of a low power reconfigurable accelerator ”,” Proc. of the ASP-DAC 2012, Jan 2012.



2011

論文誌

  1. M. Koibuchi, T. Otsuka, T. Kudoh, and H. Amano, “A switch-tagged routing methodology for pc clustes with vlan ethernet,” IEEE Trans. on Parallel and Dsitributed Systems, vol.Vol.22, no.2, pp.217-230, 2011.
  2. H. Matsutani, M. Koibuchi, D. Ikebuchi, K. Usami, H. Nakamura, and H. Amano, “Performace, area, and power evaluations of ultrafine-grained run-time power gating routers for cmps,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and systems, vol.Vol.30, no.4, pp.520-534, 2011.
  3. H. Matsutani, M. Koibuchi, H. Amano, and T. Yoshinaga, “Prediction router: A low-latency on-chip router architecture with multiple predictors,” IEEE Trans. on Computers, vol.Vol.60, no.6, pp.783-799, 2011.
  4. K. Arda, S. Iver, and H. Amano, “Design and implementation of echo instructions for an embedded processor,” IPSJ Trans. on System LSI Design Methodology, vol.Vol.4, no.0, pp.222-231, 2011.
  5. Z. Lei, D. Ilebuchi, K. Usami, M. Namiki, M. Kondo, H. Nakamura, and H. Amano, “Design and implementation fine-grained power gating on microprocessor functional units,” IPSJ Trans. on System LSI Design Methodology, vol.Vol.4, no.0, pp.182-192, 2011.
  6. Z. Lei, H. Xu, D.I. Usami, T. Sunata, M. Namiki, and H. Amano, “A leakage efficient instruction tlb design for embedded processors,” IEICE Trans. on Informations and Systems, vol.Vol.E94-D, no.8, pp.1565-1574, 2011.

国際学会

  1. M.Ozaki, and et.al., ”Cool Mega-Array: a highly energy efficient reconfigurable accelerator”, Proc. of ICFTP 2011, Dec. 2011.
  2. M.Kimura, K.Hironaka, and H.Amano, ”Reducing Power for Dynamically Reconfigurable Processor Array by Reducing Number of Reconfigurations”, Proc. of ICFTP 2011, Dec. 2011.
  3. M.Koibuchi, T.Watanabe, A.Minamihata, M.Nakao, T.Hiroyasu, H.Matsutani, and H.Amano, “Power-aware Multi-tree Ethernet for HPC Interconnects”, Proc. of ICNC 2011, Nov. 2011.
  4. A.Shitara, T.Nakahama, M.Yamada, T.Kamata, Y.Nishikawa, M.Yoshimi, and H.Amano, “”Vegeta: An Implementation and Evaluation of Development-support Middleware on Multiple OpenCL Platform”, Proc. of ICNC 2011, Nov. 2011.
  5. T.Nakahama, M.Yamada, M.Yoshimi, and H.Amano, ”Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster”, Proc. of UPDAS 2011, Nov. 2011.
  6. T.Toi, T.Awashima, M.Motomura, and H.Amano, ”Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors”, Proc. of IEEE MWSCAS 2011, Aug. 2011.
  7. T.Kamata, M.Yamada, A.Shitara, Y.Nisikawa, M.Yoshimi, and H.Amano, ”Implementation and Evaluation of Program Development Middleware for Cell Broadband Engine Clusters”,  Proc. of PDPTA 2011, July 2011.
  8. T.Akamine, K.Inakagata, Y. Osana, N.Fujita, and H.Amano, ”An Implementation of Out-Of-Order Execution System for Acceleration of Computational Fluid Dynamics on FPGAs”, Proc. of HEARTS 2011, June 2011.
  9. Abu Talip, M.S, and Amano, H., “A design of one-dimensional Euler equations for Fluid Dynamics on FPGA,” Access Spaces (ISAS), 2011 1st International Symposium on, june 2011.
  10. A.Amila, and H.Amano, ”High Speed CRC with 64-bit generator polynomial on an FPGA”, Proc. of HEARTS 2011, June 2011.
  11. H.Matsutani, Y.Take, D.Sasaki, M.Kimura, Y.Ono, Y.Nishiyama, M.Koibuchi, T.Kuroda, and H.Amano, ”A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs ”, Proc. of NoCS 2011, May 2011.
  12. N.Ozaki, and et.al, ”Silent-Data Path: A ultra on VLIW processors with fine-grained power gating”, Proc. of the COOL Chips XIV, April 2011.
  13. Y.Ishii, D. Ikebichi, and H.Amano, ”Research on VLIW processors with fine-grained power gating”, Proc. of the COOL Chips XIV (Poster), April 2011.
  14. W.Wang, Z.Lei, Y.Ohta, K.Usami, and H.Amano, ”Row-Based Power Gating on Functional Units”, Proc. of the COOL Chips XIV (Poster), April 2011.
  15. T.Yamamoto, K.Hironaka, M.Kimura, and K.Usami, ”Dynamic Vdd Switching Technique and aMapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction”, Proc. of International Conference on Advanced Reconfigurable Computing Systems 2012, March 2011.
  16. H.Amano, H.Morisita, K.Inakagata, Y.Osana, and N.Fujita, ”Execution of a Computational Fluid Dynamics Application on FLOPS-2D, a multi-FPG A platform (Invited)”, Proc. of DATE Workshop Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, March 2011.

国内研究会

  1. Y.Ishii, W.Wang, and H.Amano, ”Study of Mixed Power Gating on VLIW Processors”,  Proc. of the CPSY 2011, October 2011.
  2. W.Wang, Y.Ohta, Z.Lei, Y.Ishii, K.Usami, and H.Amano, ”Reducing Leakage Power Consumption of Functional Units with Fine-grained Power Gating”, Proc. of the SWoPP 2011, August 2011.
  3. T.Nakahama, M.Yamada, M.Yoshimi, and H.Amano, ”The proposal of performance tuning tool for Cell broadband Engine cluster”,  Proc. of the SWoPP 2011, July 2011.

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