Professor Hideharu Amano and 1st year Master student Koichiro Masuyama presented part of their research achievement in the 25th International Conference on Field-programmable Logic and Applications(FPL2015). The conference was held in London, UK, September 2-4, 2015. The title of their papers are “Reduction Calculator in an FPGA-based Switching Hub for High-performance Clusters” and “7 MOPS/Lemon-battery Image Processing Demonstration with an Ultra Low-power Reconfigurable Accelerator CMA-SOTB-2”. To view the full manuscript, please check the Publication page.