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2023
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2023

Journal

  1. Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, “A Scalable Body Bias Optimization Method Towards Low-Power CGRAs”, IEEE Micro, Vol. 43, no. 1, pp. 49-57, Jan.-Feb. 2023. DOI: 10.1109/MM.2022.3226739. [IEEE Xplore]
  2. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of CNN on Multi-FPGA Cluster”, IEICE Transactions on Information and Systems,Volume E106-D, No.7, Pages 1198-1208, 2023.
  3. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 4, pp. 532-542, April 2023, doi: 10.1109/TVLSI.2023.3237794. [IEEE Xplore]
  4. Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano, “Power Analysis and Power Modeling of Directly-connected FPGA Clusters”, IEICE Transactions (accepted).

International Conference

  1. Ziquan Qin, Kaijie Wei, Hideharu Amano and Kazuhiro Nakadai, “Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board,” 2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2023, pp.
  2. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “Verify-and-Retryable MTJ-based Nonvolatile Flip-Flops on Multi-Context CGRA,” The 31st IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) Demo Night, May. 2023.
  3. T.Okuyama, H.Amano, K.Ohkoda, M.Aono, “Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing,” Proc. on HEART23, ACM, Jun.2023.
  4. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster”, Proceedings of 11th International Symposium on Computing and Networking (CANDAR 2023), Matsue, Japan, November 2023
  5. R.Niwase, H.Hasegawa, Y.Yamaguchi, K.Wei, H.Amano, “A cost/power efficient storage system with directly connected FPGA and SATA disks,” Proc. of McSoC 2023, Dec. 2023
  6. Takumi Inage, Kensuke Iizuka, Hideharu Amano, “Board Allocation Algorithm for the Resource Management System of FiC”, Proceedings of 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), December, 2023.



2022

Awards

IEEE CEDA AJJC Academic Research Award

  • Aika Kamei, “A Variation-Aware MTJ Store Energy Estimation Model for Design Exploration of CGRA with Nonvolatile Flip-Flops” (ETNET Mar., 2022)

HEART 2022 Best Paper Award

  • Kaijie Wei, Yuki Kuno, Masatoshi Arai, and Hideharu Amano. 2022. RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. In International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2022), June, 2022

IEEE Computer Society Japan Chapter Young Author Award 2022

  • Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems.

Journal

  1. T.Shimizu, K.Ito, K.Iizuka, K.Hironaka, H.Amano, “The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System,” IEICE Transactions on Inf. & Syst., Accepted.
  2. Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai, “Weight Least Square Filter for Improving the Quality of Depth Map on FPGA”, The International Journal of Networking and Computing (IJNC), Accepted.
  3. N. Niwa, H. Amano, and M. Koibuchi, “Boosting the performance of interconnection networks by selective data compression,” IEICE Transactions on Information and Systems, vol.E105-D, no.12, 2022., Accepted.
  4. K. Wei, Y.Kuno, M.Arai, and H.Amano, “RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability”, IEICE Transactions on Information and Systems,Volume E106-D, no.3, Pages 337-348, 2022 Accepted

International Conference

  1. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings,” PDP 2022, Jan. 2022.
  2. Hajime Takishita, Yuan He, Masaaki Kondo, Hideharu Amano, “Accelerating Graph-Based SLAM on an M-KUBOS Board towards Multi-access Edge Computing”, COOLCHIPS25(Poster), April 2022
  3. Shigeyuki Takano and Hideharu Amano, “Study of General-Purpose CGRA Architecture”, COOLCHIPS25(Poster), April 2022
  4. Hou Zhongyang, Wei Kaijie, Hideharu Amano, Kazuhiro Nakadai, “Implementation of HARK Sound source localization by M-KUBOS“, COOLCHIPS25(Poster), April 2022
  5. Huang Pengyu, Wei Kaijie, Hideharu Amano, Kaori Ohkoda, Masashi Aono, “Multi-FPGA Implementation of Distributed Computing System for Solving the Transportation Optimization Problem“, COOLCHIPS25(Poster), April 2022
  6. Qin Ziquan, Wei Kaijie, Hideharu Amano, Kazuhiro Nakadai, “An implementation of Geometric High-order Dicorrelation-based Source Separation on an FPGA board”, COOLCHIPS25(Poster), April 2022
  7. Zhou Yuqing, Naoya Niwa, Hideharu Amano, “Distant-aware Compression for interconnection network of many-core systems”, COOLCHIPS25(Poster), April 2022
  8. Chen Yuchen, Wei Kaijie, Hideharu Amano, “An implementation of image filters on an FPGA board”, COOLCHIPS25(Poster), April 2022
  9. Shao Ningyu, Hiroaki Suzuki, Hideharu Amano, Wataru Takahashi, Kazutoshi Wakabayashi, “A CNN implementation on a multi-FPGA system with system-C description”, COOLCHIPS25(Poster), April 2022
  10. Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, and Hideharu Amano, “Power Analysis of Directly-connected FPGA Clusters,” 2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2022, pp. 1-6, doi: 10.1109/COOLCHIPS54332.2022.9772675.
  11. Kaijie Wei, Yuki Kuno, Masatoshi Arai, and Hideharu Amano. 2022. RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. In International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2022), June, 2022
  12. Shigeyuki Takano and Hideharu Amano, “Reconfiguration Cost for Reconfigurable Computing Architectures”, IEEE/ACIS International Fall Virtual Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, July 2022 (accepted)
  13. Yuchen Chen, Kaijie Wei, Hiroaki Nishi and Hideharu Amano, “An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board”, Proceedings of 10th International Symposium on Computing and Networking (CANDAR 2022), Himeji, Japan, November 2022
  14. Pengyu Huang, Kaijie Wei, Hideharu Amano and Masashi Aono, “Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory”, Proceedings of 13th International Workshop on Advances in Networking and Computing (WANC 2022), Himeji, Japan, November 2022
  15. Zhongyang Hou, Kaijie Wei, Hideharu Amano and Kazuhiro Nakadai, “An FPGA Implementation of HARK Sound source localization”, Proceedings of 5th Sustainable Computing Systems Workshop (SUSCW2022), Himeji, Japan, November 2022
  16. Aoi Hiruma, Kensuke Iizuka and Hideharu Amano, “Toward a training of CNNs on a multi-FPGA system”, Proceedings of 5th Sustainable Computing Systems Workshop (SUSCW2022), Himeji, Japan, November 2022



2021

Awards

MCSoC 2021 Best Paper Award

  • Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops”

CANDAR Outstanding Paper Award

  • Naoya Niwa, Hideharu Amano, Michihiro Koibuchi, “Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.

Journal

  1. Takuya Kojima, Takeharu Ikezoe, Hideharu Amano, “CubeSim: A Cycle Accurate Simulator for Multicore System with 3D SiP”, IEICE Transactions on Information and Systems, Vol.J104-D,No.04,pp.228-241,Apr. 2021.(In Japanese)[Open access] [English Abstract]
  2. Takeharu Ikezoe, Takuya Kojima, Hideharu Amano, “Recovering faulty Non-volatile Flip Flops for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Electronics. Vol.E104-C, No.6, pp.215-225, Jun. 2021. DOI:10.1587/transele.2020LHP0002. [Open access]
  3. Ryota Yasudo, Jose Gabriel Figueiredo Continho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, and Tobias Becker, “Analytical Performance Estimation for Large-scale Reconfigurable Dataflow Platforms,” ACM Transactions on Reconfigurable Technology and Systems. (Accepted)
  4. Kazuei HIRONAKA,Kensuke IIZUKA,Miho YAMAKURA,Akram BEN AHMED,and Hideharu AMANO, “Remotedynamic reconfiguration of a multi-FPGA system FiC (Flow-in-Cloud)”, IEICE Trans. Information and Systems,Vol.E104-D,No.8,pp.-,Aug. 2021. (To appear)
  5. Kaijie Wei, Koki Honda and Hideharu Amano “An implementation methodology for Neural Network on a Low-end FPGA Board”, International Journal of Networking and Computing(IJNC). Vol.11, No.2, pp.-, July. 2021. (Accepted)
  6. Koki honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano “CLAHE implementation and evaluation on a low-end FPGA board by high-level synthesis”, IEICE Trans. Information and Systems, Vol.E104-D,No.12,pp.-,Dec. 2021(Accepted)
  7. Miho Yamakura, Ryousei Takano, Akram Ben Ahmed, Midori Sugaya, Hideharu Amano “A Multi-tenant Resource Management System for Multi-FPGA Systems”, IEICE Trans. Information and Systems, Vol.E104-D,No.12,pp.-,Dec. 2021(Accepted)
  8. Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano “Improving the Performance of Circuit-switched Interconnection Network for a Multi-FPGA System”, IEICE Trans. Information and Systems, Vol.E104-D,No.12,pp.-,Dec. 2021(Accepted)
  9. Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems. [IEEE Xplore]

International Conference

  1. Hideto Kayashima and Hideharu Amano, “TCI Tester: Tester for Through Chip Interface”, The University Design Contest of The 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021), pp.107-108, January 2021
  2. Naoya Niwa, Yoshiya Shikama, Hideharu Amano, and Michihiro Koibuchi, “A Case for Low-Latency Network-on-Chip using Compression Routers”, Proc. of the 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2021), 10-12 Mar. 2021.
  3. Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto and Michihiro Koibuchi, “Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths”, Proc. of the 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2021), 10-12 Mar. 2021.
  4. Ohwada Ayaka, Takuya Kojima, and Hideharu Amano, “MENTAI: A Fully Automated CGRA Application Development Environment that Supports Hardware/Software Co-design”, Synthesis And System Integration of Mixed Information technologies(SASIMI2021), Mar. 2021.
  5. Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano, “Hybrid Network of Packet Switching and STDM in a Multi-FPGA System”, COOLCHIPS24, April 2021
  6. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of CNN on PYNQ Cluster”, COOLCHIPS24, April 2021
  7. Yuki Kameyama, Yoshiya Shikama, Naoya Niwa, Michihiro Koibuchi, Hideharu Amano, “Optimal placement of coherence directories using memory networks”, COOLCHIPS24, April 2021
  8. Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano, “Software management system of the PYNQ cluster”, COOLCHIPS24, April 2021
  9. Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano, “Multi-FPGA board design using CyberWorkBench, a high-level synthesis tool”, COOLCHIPS24, April 2021
  10. Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano, “A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool”,International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), June 2021
  11. Hideto Kayashima and Hideharu Amano, “Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.
  12. Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki and Hideharu Amano, “M-KUBOS/PYNQ Cluster for multi-access edge computing”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.
  13. Naoya Niwa, Hideharu Amano, Michihiro Koibuchi, “Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression”, 2021 Ninth International Symposium on Computing and Networking (CANDAR), November, 2021.
  14. Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno and Masatoshi Arai, “Weight Least Square Filter for Improving the Quality of Depth Map on FPGA,” 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW), 2021.
  15. Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano, “Parallel Implementation of CNN on Multi-FPGA Cluster”, The IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2021), December, 2021.
  16. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, and Kazuhiro Bessho, “Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops”, The IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2021), December, 2021.



2020

Journal

  1. Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano Hideharu, Rodney Van Meter “Extracting Success from IBM’s 20-Qubit Machines Using Error-Aware Compilation”,Journal on Emerging Technologies in Computing Systems, Vol.16, Issue 3, July 2020.
  2. Ryuta Kawano, Tyota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    “Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks,” IEICE Trans on Inf&Tech (Accepted)
  3. Yuxi Sun, Hideharu Amano, “FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks”, IEICE Trans. on Inf&Tech (Accepted)
  4. Carlos C. Cortes Torres, Ryota Yasudo and Hideharu Amano, “Body Bias Optimization for Real-Time Systems”, Journal of Low Power Electronics and Applications, Vol.10,No.1,Feb.2020.Ry
  5. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “A Generalized Theory based on the Turn Model for Deadlock-Free Irregular Networks”, IEICE Transactions on Information and Systems, Vol.E103-D, No.01, pp.101–110, Jan 2020.
  6. Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano, “GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse Grained Reconfigurable Architectures”, IEEE Transactions on Very Large Scale Integration Systems (VLSI), Vol. 28, no. 11, pp.2383-2396, Nov 2020. [IEEE Xplore][Tool available at Github]
  7. Ryota Yasudo, Hiroki Matsutani, Koji Nakano, Hideharu Amano, Michihiro Koibuchi, “Designing Low-Diameter Interconnection Networks with Multi-ported Host-Switch Graphs” The Concurrency and Computation: Practice and Experience. (Accepted)

International Conference

  1. Hideharu Amano, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Yugo Yamauchi, M.M.Imdad Ullah, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Tomotaka Shimizu, Kohei Ito, “Flow-in-Cloud: a Scalable multi-FPGA system for HPC”, HiPEAC2020 EuroEXA workshop, Jan 2020, Bologna
  2. Tomoki Shimizu, Kohei Ito, Yugo Yamauchi, Kauei Hironaka, Hideharu Amano, “Implementation of a Packet-Switching Router on a Mukti-FPGA System”, COOLCHIPS23, April 2020
  3. Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano, “Implementation of an Application Utilized Multi-Switch on a Multi-FPGA System”, COOLCHIPS23, April 2020
  4. Yoshiya Shikama, Kawano Ryuta, Akram Ben Ahmed, Hiroki Matsutani, Michiciro Koibuchi, Hideharu Amano, “Low-Latency Memory Packet Network Using Bypassing”, COOLCHIPS23, April 2020
  5. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “Compiler Framework for Spatial Mapping CGRA using LLVM”, COOLCHIPS23, April 2020
  6. Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano, “A Method of Partitioning Convolutional Layer to Multiple FPGAs”, 17th International SoC Design Conference (ISOCC), pp.25-pp.26, Oct. 2020.
  7. Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke IIzuka, Hideharu Amano, “Horizontal division of deep learning applications with all-to-all communication on a multiFPGA system”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020
  8. Kohei Ito, Kensuke IIzuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano, “Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020.
  9. Kaijie Wei, Koki Honda and Hideharu Amano, “An implementation methodology for Neural Network on a Low-end FPGA Board”, 2020 Eighth International Symposium on Computing and Networking (CANDAR), November, 2020.
  10. Manfred Orsztynowicz, Kenichi Kubota, Hideharu Amano and Takaaki Miyajima, “Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA”, 2020 Eighth International Symposium on Computing and Networking (CANDAR), November, 2020.
  11. Koki Honda, Wei Kaijie, Masatoshi Arai and Hideharu Amano. “CLAHE implementation on a low-end FPGA board by high-level synthesis”, 2020 Eighth International Symposium on Computing and Networking Workshop (CANDARW), November, 2020.



2019

Awards

COOL Chips 22 Featured Poster Award

  • Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano, ”Partial Reconfiguration Technique for a Multi-board FPGA System FiCSW”

MCSoC 2019 Best Paper Award

  • Hayate Okuhara, Ryosuke Kazami, and Hideharu Amano, “A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration”

IEEE CEDA AJJC Design Gaia Best Poster Award 2019

  • Takuya Kojima, “Evaluation of A Novel Application Mapping Framework for CGRAs”

Journal

  1. Takuya Kojima and Hideharu Amano, “A Fine-Grained Multicasting of Configuration data for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E102-D,No.7,pp.1247-1256,Jul. 2019. DOI:10.1587/transinf.2018EDP7336.

International conference

  1. Yugo Yamauchi, Kazusa Musha, Hideharu Amano, “Implementing LSTM on the multi-FPGA sytem: Flow-in-Cloud.”, COOLCHIPS22, April 2019.
  2. Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano, ”Real Chip Performance Evaluation of Inductive Coupling TCI IP”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  3. Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano, ”Partial Reconfiguration Technique for a Multi-board FPGA System FiCSW”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  4. Koki Honda, Wei Kaijie, Hideharu Amano, ”The Framework for Image Processing Aiming to Autonomous Car Using FPGA”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  5. Yasuaki Okamoto, Hideharu Amano, ”Implementation of ART algorithm with Xilinx SDAccel”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  6. Aoi Hiruma, Yugo Yamauchi, Kazusa Musha, Hideharu Amano, ”Implementation of Training Phase of Convolutional Neural Networks on a Multi-FPGA system”, Proc. of the COOLCHIPS22 (Poster), April 2019.
  7. Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, and Hideharu Amano, “An ARM-based heterogeneous FPGA accelerator for hall thruster simulation”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2019), June, 2019, Nagasaki, Japan.
  8. Yuxi Sun, Akram Ben Ahmed, and Hideharu Amano, “Acceleration of deep recurrent neural networks with an FPGA cluster”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2019), June, 2019, Nagasaki, Japan.
  9. Yamakura Miho, Hironaka Kazuei, Azegami Keita, Musha Kazusa, and Amano Hideharu, “The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2019), June, 2019, Nagasaki, Japan.
  10. Takuya Kojima and Hideharu Amano, “Refinements in Data Manipulation Method for Coarse Grained Reconfiguration Architectures”, 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2019), York, United Kingdom, July, 2019.
  11. Kazuei Hironaka, Akram Ben Ahmed, and Hideharu Amano, “Multi-FPGA Management on Flow-in-Cloud Prototype System”, 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2019), July, Toyama, Japan.
  12. Takuya Kojima, Naoki Ando, Yusuke Matsushita and Hideharu Amano, “Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA”, 29th International Conference on Field Programmable Logic and Applications (FPL), pp. 411-412, Barcelona, Spain, September, 2019. (Demo Paper)
  13. Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M M Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, and Hideharu Amano, “Demonstration of Flow-in-Cloud: A multi-FPGA system”, 29th International Conference on Field Programmable Logic and Applications (FPL), pp. 417-418, Barcelona, Spain, September, 2019. (Demo Paper)
  14. Hayate Okuhara, Ryosuke Kazami, and Hideharu Amano, “A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.32-37, Singapore, October, 2019.
  15. Koki Honda, Kaijie Wei, Hideharu Amano, “FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.53-60, Singapore, October, 2019.
  16. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo and Mitaro Namiki, “A Preliminary Evaluation of Buiding Block Computing Systems”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.312-319, Singapore, October, 2019.
  17. Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuch, Yao Hu, Hideharu Amano, “A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), pp.328-333, Singapore, October, 2019.
  18. Ryohei Tomura, Takuya Kojima, and Hideharu Amano, “A Real chip evaluation of a CNN accelerator SNACC”, Synthesis And System Integration of Mixed Information technologies(SASIMI2019), Tainan, Taiwan, October, 2019.
  19. Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano, ”Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process”, 2019 Seventh International Symposium on Computing and Networking Workshop (CANDARW), Nagasaki, Japan, November, 2019.
  20. Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, “Deadlock-Free Layered Routing for Infiniband Networks”, Proc. of the 7th International Symposium on Computing and Networking Workshops (CANDARW’19), pp.84–90, Nov 2019. [Paper] [Slide]
  21. Takeharu Ikezoe, Takuya Kojima and Hideharu Amano, “A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory,” 2019 International Conference on Field-Programmable Technology (ICFPT), Tianjin, China, 2019, pp. 81-89.



2018

Awards

COOL Chips 21 Best Poster Award

  • Kensuke Iizuka, “A multi-FPGA accelerator for GoogLeNet”

CANDAR’18 Outstanding Paper Award

  • Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, and Hideharu Amano, “k-Optimized Path Routing for High-Throughput Data Center Networks,” 2018 Sixth International Symposium on Computing and Networking (CANDAR), Takayama, 2018, pp. 99-105.

SUSCW’18 Best Paper Award

  • Hideki Shimura, Hiroyuki Noda, and Hideharu Amano, “C4: An FPGA-based Compression Algorithm for ExpEther,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 356-362.

IEEE Computer Society Young Author Award 2018

  • Ryota Yasudo

IEICE CPSY Young Presentation Award

  • Takuya Kojima “Low Power Stream Processing on a Variable Pipelined Accelerator CCSOTB2”
  • Hiroyuki Noda “ホールスラスタ内部解析用PIC法計算のArria 10 SoC FPGAへの実装”

Journal

  1. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan and Hideharu Amano, “Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E101-D, No.6, pp.1532-1540, Jun 2018. DOI: 10.1587/transinf.2017EDP7308.
  2. Keita Azegami, Hayate Okuhara and Hideharu Amano, “Body Bias Control for Renewable Energy Source with a High Inner Resistance,”, IEEE Transactions on Multi-Scale Computing Systems, 2018. (accepted)
  3. H. Okuhara, A. Ben Ahmed and H. Amano, “Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems,” in IEEE Transactions on Circuits and Systems I: Regular Papers.
    doi: 10.1109/TCSI.2018.2811504
  4. H. Okuhara, A. Ben Ahmed, J. M. Kühn and H. Amano, “Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
    doi: 10.1109/TVLSI.2018.2812893
  5. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, and Hideharu Amano, “Designing High-Performance Interconnection Networks with Host-Switch Graphs”, IEEE Transactions on Parallel and Distributed Systems, vol. 29, no. X, 2018.
    DOI: 10.1109/TPDS.2018.2864286
  6. Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “Ultra Low Power Reconfigurable Accelerator”, IEICE Tran. on Information and Systems, Vol.J101-D, No.5, pp.729-741, May. 2018. DOI: 10.14923/transinfj.2017JDP7034 (in Japanese)

International Conference

  1. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando, Mitaro Namiki, Hideharu Amano, “A Shared Memory Chip for Twin-Tower of Chips”, Proc. of The 21th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI2018),pp.353-358, March 2018.
  2. Ryosuke Kazami, Hayate Okuhara, Hideharu Amano, “Design Automation Methodology of a Critical Path Monitor for Adaptive Voltage Controls,” in Proc. of The COOLCHIPS21, pp.1-3, April 2018.
  3. Kazusa Musha, Tomohiro Kudoh and Hideharu Amano, “Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud”, Proc. of the International Simposium on Applied Reconfigurable Computing (ARC), 2018.
  4. Kazuei Hironaka, Nguyen Anh Vu Doan and Hideharu Amano, “Towards an optimized multi FPGA architecture with STDM network: a preliminary study”, Proc. of the International Simposium on Applied Reconfigurable Computing (ARC), 2018.
  5. Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, and Hideharu Amano, “Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC”, in Proc. of 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Budapest, Hungary, April 2018.
  6. Ryota Yasudo, Ana Lucia Varbanescu, Jose Gabriel Figueiredo Coutinho, Wayne Luk, and Hideharu Amano, “Performance Prediction for Large-scale Heterogeneous Platforms”, in Proc. of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, USA, April/May 2018.
  7. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano, “Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), June, 2018, Toronto, Canada.
  8. Takuya Kojima and Hideharu Amano, “A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures”, in Proc. of 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 239-242, August, 2018, Dublin, Ireland.
  9. Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, ”Adaptive Body Bias Control Scheme for Ultra Low-power Network-on-Chip Systems”, In Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-18), Hanoi, Vietnam, pp. – , September, 2018.
  10. Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, ”AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation”, In Proc. of the 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS-2018), Turin, Italy, pp. 44-51, October, 2018.
  11. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, and Hideharu Amano, “k-Optimized Path Routing for High-Throughput Data Center Networks,” 2018 Sixth International Symposium on Computing and Networking (CANDAR), Takayama, 2018, pp. 99-105.
  12. Tomohiro Totoki, Michihiro Koibuchi, and Hideharu Amano, “An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 363-369.
  13. Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, “An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 182-185.
  14. Hideki Shimura, Hiroyuki Noda, and Hideharu Amano, “C4: An FPGA-based Compression Algorithm for ExpEther,” 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, 2018, pp. 356-362.
  15. Kaijie Wei, Koki Honda and Hideharu Amano, “FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks,” 2018 International Conference on Field-Programmable Technology (FPT), 2018, pp. 425-428.
  16. Ryota Yasudo, Jose Gabriel Figueiredo Continho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, and Tobias Becker, “Performance Estimation for Exascale Reconfigurable Dataflow Platforms”, in Proc. of the International Conference on Field-Programmable Technology, Naha, Japan, December 2018.



2017

Journal

  1. A.Nomura, Y.Matsushita, J.Kadomoto, H.Matsutani, T.Kuroda, H.Amano, “Escalator Network for a
    3D Chip Stack with Inductive Coupling ThruChip Interface,” International Journal of Network and Computing, (Accepted)
  2. T.Okubo, M.Sit, H.Amano, R.Takata, R.Sakamoto, M.Kondo, “A Software Development Environment for a Multi-chip Convolutional Network Accelerator,” International Journal of Computer Application, Vol.24, No.2, June 2017.
  3. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing”, IEICE Transactions on Information and Systems, Vol.E100-D, No.8, pp.1798–1806, Aug 2017. DOI: 10.1587/transinf.2016EDP7477
  4. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano, “Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator”, IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.2828–2836, Dec 2017. DOI: 10.1587/transinf.2017PAP0013
  5. Hayate Okuhara,Yu Fujita, Kimiyoshi Usami, and Hideharu Amano, “Power Optimization Methodology for Ultra Low Power Microcontroller with Silicon on Thin BOX MOSFET”, IEEE Tran. on Very Large Scale Integration Systems, Vol.25, Issue4, 2017.
  6. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “A Layout-Oriented Routing Method for Low-Latency HPC Networks”, IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.2796-2807, Dec 2017. DOI: 10.1587/transinf.2017PAP0019

International conference

  1. T.Ohkubo, R.Takata, R.Sakamoto, M.Kondo, H.Amano, “NAMACHA: A software edevelopment environment for a mutli-chip convolutional network accelerator,” CATA2017, March, 2017.
  2. Keita Azegami, Hayate Okuhara, Hideharu Amano, “Body Bias Control for Renewable Energy Source with a High Inner Resistance”, COOLCHIPS20, April, 2017.
  3. Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita and Hideharu Amano, “Acceleration of the aggregation process in a Hall-thruster simulation using Altera SDK for OpenCL”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), June, 2017.
  4. Takahiro Kaneda, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano, “Performance Evaluation of PEACH3: Field Programmable Gate Array Switch for Tightly Coupled Accelerators,” International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), June, 2017.
  5. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amaon, “Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks,” 46th International Conference on Parallel Processing (ICPP-2017), August, 2017.
  6. Naoki Nishikawa, Hideharu Amano, Keisuke Iwai, “Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU,” 11th International Conference on Network and System Security (NSS-2017), August, 2017.
  7. Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano, “Accelerator-in-Switch: a framework for tightly couple switching hub and an accelerator with FPGA” 27th International Conference on Field Programmable Logic and Applications (FPL2017), Sept., 2017.
  8. C. Cortes, H.Amano, “Break Even Time Analysis Using Empirical Overhead Parameters for Embedded Systems on SOTB Technology,” Design of Circuits and Integrated Systems Conference, Nov. 2017
  9. H.Nakahara, N.A.V.Doan, R.Yasudo, H.Amaon, “XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs,” NOCS2017, Oct. 2017
  10. K.Usami, S.Kogure, Y.Yoshida, R.Magasaki, H.Amano, “Level-shifter Free Approach for Multi-VDD SOTB employing Adaptive Vt Modulation for pMOSFET,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Oct. 2017
  11. N.A.V.Doan, Y.Matsushita, N.Ando, H.Okuhara, H.Amano, “Multi-Objective Optimization for Application Mapping and Body Boas COntrol on a CGRA,” IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Sept. 2017
  12. R.Sakamoto, R.Takata, J.Ishii, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano, “The Design and Implementation of Scalable Deep Neural Network Accelerator Cores,”IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Sept. 2017
  13. T. Kojima, N. Ando, H. Okuhara, N. A. V. Doan and H. Amano, “Body bias optimization for variable pipelined CGRA,” 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, Sept. 2017, pp. 1-4.
  14. H.Nakahara, R.Yasudo, H.Matsutani, H.Amano, H.Koibuchi, “3D layout of Spidergon, Flattened Butterfly and Dragonfly on a chip stack with inductive coupling through chip interface,” The 14th International Symposium on Pervasive Systems, Algorithms, and Networks (I-SPAN2017), June, 2017.
  15. C.Cortes, H.Amano, “Switching Region Analysis for SOTB Technology,” 10th International Caribbean Conference on Devices, Circuits and Systems, June. 2017
  16. T. Kojima, N. Ando, H. Okuhara and H. Amano, “Glitch-aware variable pipeline optimization for CGRAs,” 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2017, pp. 1-6.
  17. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies”, Proc. of the IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS’17), pp.664–673, Dec 2017. [Paper]



2016

Awards

IPSJ Best Paper Award

  • Takaaki Miyajima, David Thomas, Hideharu Amano, “Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms”, IPSJ Transactions on System LSI Design Methodology Vol. 8 (2015) pp. 105-115

CANDAR Best Paper Award

 

 

  • Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “LOREN: A Scalable Routing Method for Layout-conscious Random Topologies”, the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.

HiPEAC Paper Award

 

  • Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel “Leveraging FDSOI through body bias domain partitioning and bias search”, DAC2016, July, 2016.

Journal

  1. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tadao Nakamura, “Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers”, IEEE Transactions on Computers. (to be published)
  2. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, and Hideharu Amano, ”Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems”, IEICE Transactions on Electronics, Vol. E99-C No. 8, pp. 909-917, August 2016.
  3. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, “Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24,No.2pp.493-506, 2016

International Conference

  1. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “LOREN: A Scalable Routing Method for Layout-conscious Random Topologies”, Proc. of the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.
  2. Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano, “On-the-fly data compression/decompression mechanism with ExpEther”, Proc. of the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.
  3. Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano, “Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface”, Proc. of the 4th International Symposium on Computing and Networking (CANDAR), Nov 2016.
  4. Carlos Cesar Cortes Torres, Hayate Okuhara, Akram Ben Ahmed, Nobuyuki Yamasaki,
    Hideharu Amano, “Analysis of Body Bias Control for Real Time Systems”, Proc. of the 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Oct. 2016.
  5. Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano, “Acceleration of Full-PIC simulation on a CPU-FPGA tightly coupled environment”, Proc. of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep 2016.
  6. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano and Hideharu Amano “Body Bias Grain Size Exploration for a Coarse Grained Reconfigurable Accelerator”, Proc. of the 26th The International Conference on Field-Programmable Logic and Applications (FPL), 2016.
  7. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel “Leveraging FDSOI through body bias domain partitioning and bias search”, DAC2016, July, 2016.
  8. Takahiro Kaneda, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano “Performance Evaluation of PEACH3: an FPGA switch for tightly coupled accelerators”, Proc. of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), 2016.
  9. Takuji Mitsuishi, Takahiro Kaneda, Hideharu Amano and Sunao Torii “Breadth-first Search on Suiren: a compact supercomputer”, Proc. of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), 2016.
  10. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, “ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free”, Proc. of the 15th IEEE/ACIS International Conference on Computer and Information Science(ICIS), 2016.
  11. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel, “Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search”, Proc. of the 53nd Design Automation Conference(DAC), 2016.
  12. Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano, “On-the-fly data compression for ExpEther NIC” , Proc. of the 19th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIX), Poster session, Apr. 2016.
  13. Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, “Randomizing Packet Memory Networks for Low-latency Processor-memory Communication,” Proc. of the 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 17-19 Feb. 2016.
  14. Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano, “Zynq Cluster for CFD Parametric Survey”, Proc. of the International Simposium on Applied Reconfigurable Computing (ARC), 2016.(to appear)



2015

Awards

Best Paper Award

  • Yu Fujita, Hayate Okuhara, Koichiro Masuyama, and Hideharu Amano, “Power optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB”, Proc. of The Third International Symposium on Computing and Networking (CANDAR), Dec 2015
  • Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Masayuki Umemura and Hideharu Amano, “Off-loading LET generation to PEACH2: A switching hub for high performance GPU clusters”, Proc. of the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART), May 2015. (Best paper award)

Best Poster Award

  • Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “Ultra Low Power Reconfigurable Accelerator CMA-SOTB-2”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.

Journal

  1. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham “A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode,” Vol.E98-C No.7, pp.536-543. 2015.
  2. A.Koshiba, M.Wada, R.Sakamoto, M.Sato, T.Kosaka, K.Usami, H.Amano, M.Kondo, H.Nakamura, M.Namiki, “A Fine-grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Unit”,IEICE Transactions. on Electronics, Vol.E98-C, No.7、pp.559-568,2015.
  3. Takaaki Miyajima, David Thomas, Hideharu Amano, “Courier: A toolchain for acceleration on Heterogeneous Platforms
  4. Takaaki Miyajima, David Thomas, Hideharu Amano, “A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms”, Journal of Information Processing, vol.23, no.2, pp.153-162, 2015.

International Conference

  1. Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano, “Trax Solver on Zynq with Deep Q-Network”, Proc. of the International Conference on Field-Programmable Technology (ICFPT), December 2015.
  2. Koichiro Masuyama, Yu Fujita, Hayate Okuhara and Hideharu Amano, “A 297MOPS/0.4mW Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA-SOTB-2”, Proc. of The 10th International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2015.
  3. Yu Fujita, Hayate Okuhara, Koichiro Masuyama, and Hideharu Amano, “Power optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB”, Proc. of The Third International Symposium on Computing and Networking (CANDAR), pp.xxx-xxx, 2015.(to appear)
  4. Akio Nomura,Yu Fujita, Hiroki Matsutani,and Hideharu Amano, “3D Shared Bus Architecture Using Inductive Coupling Interconnect”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.xxx-xxx, Sep 2015.
  5. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.xxx-xxx, Sep 2015.
  6. Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano, “REDUCTION CALCULATIOR IN AN FPGA BASED SWITCHING HUB FOR HIGH PERFORMANCE CLUSTERS”, Proc. of the 25th International Conference on Field-programmable Logic and Applications (FPL), September 2015.
  7. Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “7 MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2”, Proc. of the 25th International Conference on Field-programmable Logic and Applications (FPL), September 2015.
  8. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano and Tadao Nakamura, “On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck”, Proc. of the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), September 2015.
  9. Seiichi Tade, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, “A Metamorphotic Network-on-Chip for Various Types of Parallel Applications”, Proc. of the IEEE International Conferene on Application-specific Systems, Architectures and Processors (ASAP), July 2015.
  10. Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, and Hideharu Amano, “An Optimal Power Supply And Body Bias Voltage for a Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET”, Proc. of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015.
  11. Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan and Hideharu Amano, “Breadth First Search on Cost-efficient Multi-GPU Systems”, Proc. of the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART), May 2015. (to appear)
  12. Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Masayuki Umemura and Hideharu Amano, “Off-loading LET generation to PEACH2: A switching hub for high performance GPU clusters”, Proc. of the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART), May 2015. (to appear) (Best paper candidate)
  13. Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmannz, Wolfgang Rosenstiel, “Fined-Grained Body Biasing for Frequency Scaling in Advanced SOI Processes”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Apr. 2015.
  14. Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano, “A Leakage Current Monitor Circuit Using Silicon on Thin BOX MOSFET for Dynamic Back Gate Bias Control”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Apr. 2015.
  15. Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano, “Ultra Low Power Reconfigurable Accelerator CMA-SOTB-2”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015. (Best poster award)
  16. Takahiro Kaneda, Takuji Mitsuishi, Yuki Katsuta, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku, “Parallel Processing of Graph Search by Tightly Coupled Accelerator”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  17. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, “Staggered Stacking: Connecting Many Small Chips Using ThruChip Interface”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  18. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, “3D Bus Architecture using Inductive Coupling ThruChip-Interface”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  19. Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Takuji Mitsuishi, Naru Sugimoto, Hideharu Amano, “Off-loading LET generator in PEACH2 : A Switching Hub for High Performance GPU Clusters”, Proc. of the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr. 2015.
  20. Mao Hatto, Takaaki Miyajima, Hideharu Amano, “Data Reduction and Parallelization for Human Detection System”, Proc. of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.134-139, Mar. 2015.
  21. Hayate Okuhara, Hideharu Amano, “Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET”, Proc. of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.299-304, Mar. 2015.
  22. Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel, “Spatial and temporal granularity limits of body biasing in UTBB-FDSOI”, Proc. of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2015.
  23. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, “Optimized Core-links for Low-latency NoCs”, Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pp.172-176, Mar. 2015.



2014

Awards

Best Paper Award

  • Yu Fujita, Kimiyoshi Usami, Hideharu Amano, “A Thermal Management System for Building Block Computing System,” Proc. of Enbedded Multicore/Many-core System on Chips, September 2014.

Featured Poster Award

  • Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano, “Voltage control considering the chip temperature in the three-dimensional stacked multi-core processors,” Proc. of the COOL Chips XVII (Poster), April 2014.
  • Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,
    “A Configurable Switch Mechanism for Random NoCs,” Proc. of the COOL Chips XVII (Poster), April 2014.

Journal

  1. Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano, “A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA”, International Journal of Networking and Computing, Vol.4, No.2, 2014.
  2. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda and Hideharu Amano, “3D NoC with Inductive-Coupling Links for Building-Block SiPs”, IEEE Transaction on Computers, Vol.63, No.3, pp.748–763, March 2014. (DOI:10.1109/TC.2012.249)
  3. Takayuki AKAMINE, Mohamad Sofian ABU TALIP, Yasunori OSANA, Naoyuki FUJITA, Hideharu AMANO,
    Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh, IEICE TRANSACTIONS on Information and Systems Vol.E97-D No.5 pp.1225-1234
  4. Zhang Hao, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,
    Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs, IPSJ Transaction
    on System LSI Design Methodology, Vol.7 pp,27-36.

International Conference

  1. Yu Fujita, Koichiro Masuyama, Hideharu Amano, “Image processing by A 0.3 V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery”, roc. of the International Conference on Field-Programmable Technology (ICFPT), December 2014.
  2. Naru Sugimoto, Hideharu Amano, “Hardware/software co-design architecture for Blokus Duo solver”, Proc. of the International Conference on Field-Programmable Technology (ICFPT), December 2014.
  3. Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, “A Preliminarily Evaluation of PEACH3: A Switching Hub for Tightly Coupled Accelerators”, Proc. of the International Symposium on Computing and Networking (CANDAR), December 2014.
  4. Dipikarani Mishra, Mao Hatto, Takuya Kuhara, Yasunori Osana, Naoyuki Fujita, Hideharu Amano, “FPGA Implementation of Viscous Function in a Package for Computational Fluid Dynamics”, Proc. of the International Symposium on Computing and Networking (CANDAR), December 2014.
  5. Yu Fujita, Kimiyoshi Usami, Hideharu Amano, “A Thermal Management System for Building Block Computing System,” Proc. of Enbedded Multicore/Many-core System on Chips, September 2014.
  6. Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura, “Design of a Low Power NoC Router using Marching Memory Through type,” Proc. of the 8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), September 2014.(DOI:10.1109/NOCS.2014.7008769)
  7. Toru Katagiri, Hideharu Amano, “A high speed design and implementation of dynamically reconfigurable processor using 28nm SOI technology”, Proc. of Field Programable Logic and Applications (FPL), September 2014.
  8. Honlian Su, Yu Fujita, Hideharu Amano, “Body Bias Control for a Coarse Grained Reconfigurable Accelerator Implemented with Silicon on Thin BOX Technology,” Proc. of Field Programable Logic and Applications (FPL), September 2014.
  9. Hideharu Amano, “Block Computing Systems with Wireless Inductive Through Chip Interface”, Proc. of the 6th Workshop on Design for 3D Silicon Integration (Invited), June 2014.
  10. Johannes Maximilian Kühn, Hideharu Amano, Toru Katagiri, Wolfgang Rosenstiel, “Leakage Reduction using Coarse-Grained Static Body Biasing in a Dynamically Reconfigurable Processor”, Proc. of Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June 2014.
  11. Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano, “Accelerating Breadth First Search on GPU-BOX,” Proc. of Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June 2014.
  12. Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura , ”A low power NoC router using the marching memory through type,” Proc. of the COOL Chips XVII , Apr 2014. (DOI:10.1109/CoolChips.2014.6842960)
  13. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,
    “A Configurable Switch Mechanism for Random NoCs,” Proc. of the COOL Chips XVII (Poster), April 2014.
  14. Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano, “Voltage control considering the chip temperature in the three-dimensional
    stacked multi-core processors,” Proc. of the COOL Chips XVII (Poster), April 2014.
  15. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku, “Task Level Pipelining on Multiple Accelerators via FPGA Switch,” Proc. of Parallel and Distributed Computing and Networks, February 2014.



2013

Award

Best Paper Award

  • Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, “A Case for Wireless 3D NoCs for CMPs”, The 18th Asia and South Pacific Design Automation Conference(ASPDAC’13), Jan 2013.

Best Poster Award

  • Y.Koizumi, N.Miura, Y.Take, H.Matsutani, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura, “Performance and Energy Optimization of a Heterogeneous Multi-Core Processor with Inductive Coupling Links,” CoolChips XVI,April, 2013.

電子情報通信学会コンピュータシステム研究会若手研究賞

  • 伊澤麻衣 低消費電力アクセラレータCMAのコプロセッサ化について 2012年8月研究会
  • 宮島敬明 OpenCVとGPUを対象としたランタイムバイナリアクセラレーション機構の試作と評価 2012年10月研究会
  • 河野隆太 複数ホストリンクを用いたNoC向け低遅延トポロジ 2013年4月研究会

Journal

 

 

  1. M. Sofian Abu Talip, T. Akamine, M.Hatto, Y.Osana, H.Amano, “Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration”, International Journal of Networking and Computing, Vol.3, No.2, pp.289–306, Aug 2013.
  2. A.Akagic, H.Amano, “Design and Implementation of IP-based iSCSI Offload Engine on an FPGA”, IPSJ Trans. System LSI Design Methodology, No.6,pp.112–121,Aug 2013.
  3. A.Akagic, H.Amano, “High-Speed Fully-Adaptable CRC Accelerators”, IEICE Trans. Inf. and Syst.,E96-D,No.6,pp.1299-1308, Jun,2013.
  4. H.Nakamura, W.Wang, Y.Ohta, K.Usami, H.Amano, M.Kondo, M.Namiki, “Fine-Grained Run-Time Power Gating though Co-Optimization of Circuit, Architecture and System Sofware Design”, IEICE Trans. Electron., E-96C, No.4, pp.404-412, Apr 2013.

International Conference

  1. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, and Hideharu Amano, “Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing,” Proc. of Field-Programmable Technology, Dec 2013.
  2. Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, and Hideharu Amano, “A co-processor design of an energy efficient reconfigurable accelerator CMA,” CANDAR 2013, Dec  2013.
  3. K.Kitamori, H.Su, H.Amano, “Power optimization of a micro-controller with Silicon On Thin Buried Oxide,” SASIMI 2013, Oct 2013.
  4. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, ”Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive Coupling Links”, Proc. of the COOL Chips XVI , Apr 2013.
  5. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, ”Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture”, Proc. of the 7th ACM/IEEE International Symposium on Networks-on-Chip(NOCS’13), Apr 2013.
  6. Nobuyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, and Hiroshi Nakamura, ”A Scalable 3D Heterogeneous Multi-Core Processor with Inductive Coupling ThruChip Interface”, Proc. of the COOL Chips XVI , Apr 2013.
  7. Rie Uno, Nobuaki Ozaki, Hideharu Amano, ”Research of PE Array Connection Network for Cool Mega-Array”, Proc. of Int. Workshop on Renewable Computing Systems(WReCS’13), Mar 2013.
  8. Daiki Kugami, Takaaki Miyajima, and Hideharu Amano, ”A circuit division method for High Level synthesis on Multi-FPGA systems”, Proc. of Int. Workshop on Renewable Computing Systems(WReCS’13), Mar 2013.
  9. Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, and Hideharu Amano,  ”An FPGA Acceleration for the Kd-tree Search in Photon Mapping”, Proc. of Int. Synposium on Advanced Reconfigurable Systems, Mar 2013.
  10. Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Michihiro Koibuchi, Tadahiro Kuroda, and Hideharu Amano, ”A Case for Wireless 3D NoCs for CMPs”, Proc. of The 18th Asia and South Pacific Design Automation Conference(ASPDAC’13), Jan 2013.



2012

Journal

  1. 小崎信明, 宇野理恵, 天野英晴, “超低消費電力粗粒度再構成アクセラレータCMAのPEアレイアーキテクチャの最適化”, 情報処理学会論文誌：コンピューティングシステム, Vol.5, No.5, pp10–22, Oct 2012.
  2. 石井義史, 王蔚涵, 天野英晴, “VLIW型プロセッサにおけるMixed Power Gatingの研究”,  情報処理学会論文誌：コンピューティングシステム, Vol.5, No.5, pp23–32, Oct 2012.
  3. Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano, “Partial reconfiguration of flux limiter functions in MUSCL scheme using FPGA”, IEICE Transactions on Information & Systems, E-95D, No.10, pp2369–2376, Oct 2012.

International Conference

  1. Amila Akagic, and Hideharu Amano, “”A Study of Adaptive co-processors for Cyclic Redundancy Checks on an FPGA”,” Proc. of the International Conference on Field-Programmable Technology, Dec 2012.
  2. Yusuke Koizumi, Eiichi Sasaki, Daisuke Sasaki, Yasuhiro Take, Mitaro Namiki, Tadahiro Kuroda, and Hideharu Amano, “”CMA-CUBE: A SCALABLE RECONFIGURABLE ACCELERATOR WITH 3-D WIRELESS INDUCTIVE COUPLING INTERCONNECT”,” Proc. of the International Conference on Field Programmable Logic and Application, Oct 2012.
  3. Toru Katagiri, Kazuei Hironaka, and Hideharu Amano, “”Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array”,” Proc. of the WReCS 2012 , Sep 2012.
  4.  Shimpei Nomura, Tetusya Nakahama, Junichi Higuchi, Jun Suzuki, Takashi Yoshikawa , and Hideharu Amano, “”The multi-GPU System with ExpEther”,” Proc. of the PDPTA, July 2012.
  5. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D.Frank Hsu, and Henri Casanova, “”A Case for Random Shortcut Topologies for HPC Interconnects”,” Proc. of the ISCA, June 2012.
  6. Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, and Hideharu Amano, “”Trade-off analysis of Fine-grained Power Gating Methods for Functional Units in a CPU ”,” Proc. of the COOL Chips XV , April 2012.
  7. Toru Katagiri, Kazuei Hironaka, and Hideharu Amano, “”Extension of memory controller equipped with MuCCRA-3”,” Proc. of the COOL Chips XV (Poster), April 2012.
  8. Yusuke Koizumi, Eiichi Sasaki, Mitaro Namiki, and Hideharu Amano, “”Application Development for a Heterogeneous Multi-Core Processor”,” Proc. of the COOL Chips XV (Poster), April 2012.
  9. Rie Uno, Nobuaki Ozaki, and Hideharu Amano, “”Design Exploration of PE Array Networks for Cool Mega Array”,” Proc. of the COOL Chips XV (Poster), April 2012.
  10. Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, and Hideharu Amano, “” Cost effective implementation of flux limiter functions using partial reconfiguration ”,” Proc. of the ARC 2012, Mar 2012.
  11. Eiichi Sasaki, Daisuke Sasaki, Ikan Wang, Yusuke Koizumi, and Hideharu Amano, “” Message Passing Direct Memory Access Transfer Method for Inter-Chip Network ”,” Proc. of SASIMI 2012, March 2012.
  12. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, and Hideharu Amano, “” Vertical link on/off control methods for wireless 3-D NoCs ”,” Proc. of the ARCS 2012, Feb 2012.
  13. Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, and Hideharu Amano, “” CMA-2 : The second prototype of a low power reconfigurable accelerator ”,” Proc. of the ASP-DAC 2012, Jan 2012.



2011

Journal

  1. M. Koibuchi, T. Otsuka, T. Kudoh, and H. Amano, “A switch-tagged routing methodology for pc clustes with vlan ethernet,” IEEE Trans. on Parallel and Dsitributed Systems, vol.Vol.22, no.2, pp.217-230, 2011.
  2. H. Matsutani, M. Koibuchi, D. Ikebuchi, K. Usami, H. Nakamura, and H. Amano, “Performace, area, and power evaluations of ultrafine-grained run-time power gating routers for cmps,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and systems, vol.Vol.30, no.4, pp.520-534, 2011.
  3. H. Matsutani, M. Koibuchi, H. Amano, and T. Yoshinaga, “Prediction router: A low-latency on-chip router architecture with multiple predictors,” IEEE Trans. on Computers, vol.Vol.60, no.6, pp.783-799, 2011.
  4. K. Arda, S. Iver, and H. Amano, “Design and implementation of echo instructions for an embedded processor,” IPSJ Trans. on System LSI Design Methodology, vol.Vol.4, no.0, pp.222-231, 2011.
  5. Z. Lei, D. Ilebuchi, K. Usami, M. Namiki, M. Kondo, H. Nakamura, and H. Amano, “Design and implementation fine-grained power gating on microprocessor functional units,” IPSJ Trans. on System LSI Design Methodology, vol.Vol.4, no.0, pp.182-192, 2011.
  6. Z. Lei, H. Xu, D.I. Usami, T. Sunata, M. Namiki, and H. Amano, “A leakage efficient instruction tlb design for embedded processors,” IEICE Trans. on Informations and Systems, vol.Vol.E94-D, no.8, pp.1565-1574, 2011.

International Conference

  1. M.Ozaki, and et.al., ”Cool Mega-Array: a highly energy efficient reconfigurable accelerator”, Proc. of ICFTP 2011, Dec. 2011.
  2. M.Kimura, K.Hironaka, and H.Amano, ”Reducing Power for Dynamically Reconfigurable Processor Array by Reducing Number of Reconfigurations”, Proc. of ICFTP 2011, Dec. 2011.
  3. M.Koibuchi, T.Watanabe, A.Minamihata, M.Nakao, T.Hiroyasu, H.Matsutani, and H.Amano, “Power-aware Multi-tree Ethernet for HPC Interconnects”, Proc. of ICNC 2011, Nov. 2011.
  4. A.Shitara, T.Nakahama, M.Yamada, T.Kamata, Y.Nishikawa, M.Yoshimi, and H.Amano, “”Vegeta: An Implementation and Evaluation of Development-support Middleware on Multiple OpenCL Platform”, Proc. of ICNC 2011, Nov. 2011.
  5. T.Nakahama, M.Yamada, M.Yoshimi, and H.Amano, ”Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster”, Proc. of UPDAS 2011, Nov. 2011.
  6. T.Toi, T.Awashima, M.Motomura, and H.Amano, ”Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors”, Proc. of IEEE MWSCAS 2011, Aug. 2011.
  7. T.Kamata, M.Yamada, A.Shitara, Y.Nisikawa, M.Yoshimi, and H.Amano, ”Implementation and Evaluation of Program Development Middleware for Cell Broadband Engine Clusters”,  Proc. of PDPTA 2011, July 2011.
  8. T.Akamine, K.Inakagata, Y. Osana, N.Fujita, and H.Amano, ”An Implementation of Out-Of-Order Execution System for Acceleration of Computational Fluid Dynamics on FPGAs”, Proc. of HEARTS 2011, June 2011.
  9. Abu Talip, M.S, and Amano, H., “A design of one-dimensional Euler equations for Fluid Dynamics on FPGA,” Access Spaces (ISAS), 2011 1st International Symposium on, june 2011.
  10. A.Amila, and H.Amano, ”High Speed CRC with 64-bit generator polynomial on an FPGA”, Proc. of HEARTS 2011, June 2011.
  11. H.Matsutani, Y.Take, D.Sasaki, M.Kimura, Y.Ono, Y.Nishiyama, M.Koibuchi, T.Kuroda, and H.Amano, ”A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs ”, Proc. of NoCS 2011, May 2011.
  12. N.Ozaki, and et.al, ”Silent-Data Path: A ultra on VLIW processors with fine-grained power gating”, Proc. of the COOL Chips XIV, April 2011.
  13. Y.Ishii, D. Ikebichi, and H.Amano, ”Research on VLIW processors with fine-grained power gating”, Proc. of the COOL Chips XIV (Poster), April 2011.
  14. W.Wang, Z.Lei, Y.Ohta, K.Usami, and H.Amano, ”Row-Based Power Gating on Functional Units”, Proc. of the COOL Chips XIV (Poster), April 2011.
  15. T.Yamamoto, K.Hironaka, M.Kimura, and K.Usami, ”Dynamic Vdd Switching Technique and aMapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction”, Proc. of International Conference on Advanced Reconfigurable Computing Systems 2012, March 2011.
  16. H.Amano, H.Morisita, K.Inakagata, Y.Osana, and N.Fujita, ”Execution of a Computational Fluid Dynamics Application on FLOPS-2D, a multi-FPG A platform (Invited)”, Proc. of DATE Workshop Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, March 2011.

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